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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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569f75bd02
hasn't been an actual bug, so it's more a change to be 100% compliant with the requirements of the architecture spec. Similar fix to mask_mips_irq where there was a slightly less theoretical chance of getting hit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*
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* This file define the irq handler for MIPS CPU interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Almost all MIPS CPUs define 8 interrupt sources. They are typically
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* level triggered (i.e., cannot be cleared from CPU; must be cleared from
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* device). The first two are software interrupts which we don't really
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* use or support. The last one is usually the CPU timer interrupt if
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* counter register is present or, for CPUs with an external FPU, by
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* convention it's the FPU exception interrupt.
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*
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* Don't even think about using this on SMP. You have been warned.
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*
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* This file exports one global function:
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* void mips_cpu_irq_init(int irq_base);
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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static int mips_cpu_irq_base;
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static inline void unmask_mips_irq(unsigned int irq)
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{
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set_c0_status(0x100 << (irq - mips_cpu_irq_base));
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irq_enable_hazard();
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}
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static inline void mask_mips_irq(unsigned int irq)
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{
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clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
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irq_disable_hazard();
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}
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static inline void mips_cpu_irq_enable(unsigned int irq)
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{
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unsigned long flags;
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local_irq_save(flags);
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unmask_mips_irq(irq);
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local_irq_restore(flags);
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}
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static void mips_cpu_irq_disable(unsigned int irq)
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{
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unsigned long flags;
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local_irq_save(flags);
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mask_mips_irq(irq);
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local_irq_restore(flags);
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}
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static unsigned int mips_cpu_irq_startup(unsigned int irq)
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{
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mips_cpu_irq_enable(irq);
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return 0;
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}
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#define mips_cpu_irq_shutdown mips_cpu_irq_disable
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for mips_cpu_irq_end.
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*/
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static void mips_cpu_irq_ack(unsigned int irq)
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{
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/* Only necessary for soft interrupts */
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clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
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mask_mips_irq(irq);
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}
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static void mips_cpu_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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unmask_mips_irq(irq);
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}
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static hw_irq_controller mips_cpu_irq_controller = {
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.typename = "MIPS",
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.startup = mips_cpu_irq_startup,
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.shutdown = mips_cpu_irq_shutdown,
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.enable = mips_cpu_irq_enable,
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.disable = mips_cpu_irq_disable,
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.ack = mips_cpu_irq_ack,
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.end = mips_cpu_irq_end,
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};
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void __init mips_cpu_irq_init(int irq_base)
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{
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int i;
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/* Mask interrupts. */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP);
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for (i = irq_base; i < irq_base + 8; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].handler = &mips_cpu_irq_controller;
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}
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mips_cpu_irq_base = irq_base;
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}
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