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b3980e4852
kprobes manipulates the interrupted PSTATE for single step, and doesn't restore it. Thus, if we put a kprobe where the pstate.D (debug) masked, the mask will be cleared after the kprobe hits. Moreover, in the most complicated case, this can lead a kernel crash with below message when a nested kprobe hits. [ 152.118921] Unexpected kernel single-step exception at EL1 When the 1st kprobe hits, do_debug_exception() will be called. At this point, debug exception (= pstate.D) must be masked (=1). But if another kprobes hits before single-step of the first kprobe (e.g. inside user pre_handler), it unmask the debug exception (pstate.D = 0) and return. Then, when the 1st kprobe setting up single-step, it saves current DAIF, mask DAIF, enable single-step, and restore DAIF. However, since "D" flag in DAIF is cleared by the 2nd kprobe, the single-step exception happens soon after restoring DAIF. This has been introduced by commit7419333fa1("arm64: kprobe: Always clear pstate.D in breakpoint exception handler") To solve this issue, this stores all DAIF bits and restore it after single stepping. Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Fixes:7419333fa1("arm64: kprobe: Always clear pstate.D in breakpoint exception handler") Reviewed-by: James Morse <james.morse@arm.com> Tested-by: James Morse <james.morse@arm.com> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
113 lines
2.6 KiB
C
113 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 ARM Ltd.
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*/
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#ifndef __ASM_DAIFFLAGS_H
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#define __ASM_DAIFFLAGS_H
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#include <linux/irqflags.h>
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#include <asm/arch_gicv3.h>
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#include <asm/cpufeature.h>
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#define DAIF_PROCCTX 0
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#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
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#define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT)
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#define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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/* mask/save/unmask/restore all exceptions, including interrupts. */
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static inline void local_daif_mask(void)
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{
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WARN_ON(system_has_prio_mask_debugging() &&
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(read_sysreg_s(SYS_ICC_PMR_EL1) == (GIC_PRIO_IRQOFF |
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GIC_PRIO_PSR_I_SET)));
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asm volatile(
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"msr daifset, #0xf // local_daif_mask\n"
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:
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:
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: "memory");
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/* Don't really care for a dsb here, we don't intend to enable IRQs */
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if (system_uses_irq_prio_masking())
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gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
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trace_hardirqs_off();
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}
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static inline unsigned long local_daif_save(void)
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{
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unsigned long flags;
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flags = read_sysreg(daif);
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if (system_uses_irq_prio_masking()) {
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/* If IRQs are masked with PMR, reflect it in the flags */
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if (read_sysreg_s(SYS_ICC_PMR_EL1) != GIC_PRIO_IRQON)
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flags |= PSR_I_BIT;
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}
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local_daif_mask();
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return flags;
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}
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static inline void local_daif_restore(unsigned long flags)
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{
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bool irq_disabled = flags & PSR_I_BIT;
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WARN_ON(system_has_prio_mask_debugging() &&
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!(read_sysreg(daif) & PSR_I_BIT));
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if (!irq_disabled) {
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trace_hardirqs_on();
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if (system_uses_irq_prio_masking()) {
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gic_write_pmr(GIC_PRIO_IRQON);
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dsb(sy);
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}
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} else if (system_uses_irq_prio_masking()) {
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u64 pmr;
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if (!(flags & PSR_A_BIT)) {
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/*
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* If interrupts are disabled but we can take
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* asynchronous errors, we can take NMIs
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*/
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flags &= ~PSR_I_BIT;
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pmr = GIC_PRIO_IRQOFF;
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} else {
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pmr = GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET;
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}
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/*
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* There has been concern that the write to daif
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* might be reordered before this write to PMR.
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* From the ARM ARM DDI 0487D.a, section D1.7.1
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* "Accessing PSTATE fields":
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* Writes to the PSTATE fields have side-effects on
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* various aspects of the PE operation. All of these
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* side-effects are guaranteed:
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* - Not to be visible to earlier instructions in
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* the execution stream.
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* - To be visible to later instructions in the
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* execution stream
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*
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* Also, writes to PMR are self-synchronizing, so no
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* interrupts with a lower priority than PMR is signaled
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* to the PE after the write.
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*
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* So we don't need additional synchronization here.
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*/
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gic_write_pmr(pmr);
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}
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write_sysreg(flags, daif);
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if (irq_disabled)
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trace_hardirqs_off();
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}
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#endif
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