mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 17:37:10 +07:00
2b468ef0e7
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> |
||
|---|---|---|
| .. | ||
| bcm47xxsflash.c | ||
| bcm47xxsflash.h | ||
| block2mtd.c | ||
| docg3.c | ||
| docg3.h | ||
| elm.c | ||
| Kconfig | ||
| lart.c | ||
| m25p80.c | ||
| Makefile | ||
| ms02-nv.c | ||
| ms02-nv.h | ||
| mtd_dataflash.c | ||
| mtdram.c | ||
| phram.c | ||
| pmc551.c | ||
| slram.c | ||
| spear_smi.c | ||
| sst25l.c | ||