mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 05:15:11 +07:00
d6e81845b7
Since commit 6f888e7bc7bd58 ("clk: meson: clk-pll: add enable bit") our PLLs also support the "enable" bit. Currently meson_clk_pll_enable unconditionally resets the PLL, enables it, takes it out of reset and waits until it is locked. This works fine for our current clock trees. However, there will be a problem once we allow modifications to sys_pll on Meson8, Meson8b and Meson8m2 (which will be required for CPU frequency scaling): the CPU clock is derived from the sys_pll clock. Once clk_enable is called on the CPU clock this will be propagated by the common clock framework up until the sys_pll clock. If we reset the PLL unconditionally in meson_clk_pll_enable the CPU will be stopped (on Meson8, Meson8b and Meson8m2). To prevent this we simply check if the PLL is already enabled and do reset the PLL if it's already enabled and locked. Now that we have a utility function to check whether the PLL is enabled we can also pass that to our clk_ops to let the common clock framework know about the status of the hardware clock. For now this is of limited use since the only common clock framework's internal "disabled unused clocks" mechanism checks for this. Everything else still uses the ref-counting (internal to the common clock framework) when clk_enable is called. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181115224048.13511-2-martin.blumenstingl@googlemail.com
317 lines
8.0 KiB
C
317 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2015 Endless Mobile, Inc.
|
|
* Author: Carlo Caione <carlo@endlessm.com>
|
|
*
|
|
* Copyright (c) 2018 Baylibre, SAS.
|
|
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
|
*/
|
|
|
|
/*
|
|
* In the most basic form, a Meson PLL is composed as follows:
|
|
*
|
|
* PLL
|
|
* +--------------------------------+
|
|
* | |
|
|
* | +--+ |
|
|
* in >>-----[ /N ]--->| | +-----+ |
|
|
* | | |------| DCO |---->> out
|
|
* | +--------->| | +--v--+ |
|
|
* | | +--+ | |
|
|
* | | | |
|
|
* | +--[ *(M + (F/Fmax) ]<--+ |
|
|
* | |
|
|
* +--------------------------------+
|
|
*
|
|
* out = in * (m + frac / frac_max) / n
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/err.h>
|
|
#include <linux/io.h>
|
|
#include <linux/math64.h>
|
|
#include <linux/module.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/string.h>
|
|
|
|
#include "clkc.h"
|
|
|
|
static inline struct meson_clk_pll_data *
|
|
meson_clk_pll_data(struct clk_regmap *clk)
|
|
{
|
|
return (struct meson_clk_pll_data *)clk->data;
|
|
}
|
|
|
|
static unsigned long __pll_params_to_rate(unsigned long parent_rate,
|
|
const struct pll_params_table *pllt,
|
|
u16 frac,
|
|
struct meson_clk_pll_data *pll)
|
|
{
|
|
u64 rate = (u64)parent_rate * pllt->m;
|
|
|
|
if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
|
|
u64 frac_rate = (u64)parent_rate * frac;
|
|
|
|
rate += DIV_ROUND_UP_ULL(frac_rate,
|
|
(1 << pll->frac.width));
|
|
}
|
|
|
|
return DIV_ROUND_UP_ULL(rate, pllt->n);
|
|
}
|
|
|
|
static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
struct pll_params_table pllt;
|
|
u16 frac;
|
|
|
|
pllt.n = meson_parm_read(clk->map, &pll->n);
|
|
pllt.m = meson_parm_read(clk->map, &pll->m);
|
|
|
|
frac = MESON_PARM_APPLICABLE(&pll->frac) ?
|
|
meson_parm_read(clk->map, &pll->frac) :
|
|
0;
|
|
|
|
return __pll_params_to_rate(parent_rate, &pllt, frac, pll);
|
|
}
|
|
|
|
static u16 __pll_params_with_frac(unsigned long rate,
|
|
unsigned long parent_rate,
|
|
const struct pll_params_table *pllt,
|
|
struct meson_clk_pll_data *pll)
|
|
{
|
|
u16 frac_max = (1 << pll->frac.width);
|
|
u64 val = (u64)rate * pllt->n;
|
|
|
|
if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
|
|
val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
|
|
else
|
|
val = div_u64(val * frac_max, parent_rate);
|
|
|
|
val -= pllt->m * frac_max;
|
|
|
|
return min((u16)val, (u16)(frac_max - 1));
|
|
}
|
|
|
|
static bool meson_clk_pll_is_better(unsigned long rate,
|
|
unsigned long best,
|
|
unsigned long now,
|
|
struct meson_clk_pll_data *pll)
|
|
{
|
|
if (!(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
|
|
MESON_PARM_APPLICABLE(&pll->frac)) {
|
|
/* Round down */
|
|
if (now < rate && best < now)
|
|
return true;
|
|
} else {
|
|
/* Round Closest */
|
|
if (abs(now - rate) < abs(best - rate))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static const struct pll_params_table *
|
|
meson_clk_get_pll_settings(unsigned long rate,
|
|
unsigned long parent_rate,
|
|
struct meson_clk_pll_data *pll)
|
|
{
|
|
const struct pll_params_table *table = pll->table;
|
|
unsigned long best = 0, now = 0;
|
|
unsigned int i, best_i = 0;
|
|
|
|
if (!table)
|
|
return NULL;
|
|
|
|
for (i = 0; table[i].n; i++) {
|
|
now = __pll_params_to_rate(parent_rate, &table[i], 0, pll);
|
|
|
|
/* If we get an exact match, don't bother any further */
|
|
if (now == rate) {
|
|
return &table[i];
|
|
} else if (meson_clk_pll_is_better(rate, best, now, pll)) {
|
|
best = now;
|
|
best_i = i;
|
|
}
|
|
}
|
|
|
|
return (struct pll_params_table *)&table[best_i];
|
|
}
|
|
|
|
static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *parent_rate)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
const struct pll_params_table *pllt =
|
|
meson_clk_get_pll_settings(rate, *parent_rate, pll);
|
|
unsigned long round;
|
|
u16 frac;
|
|
|
|
if (!pllt)
|
|
return meson_clk_pll_recalc_rate(hw, *parent_rate);
|
|
|
|
round = __pll_params_to_rate(*parent_rate, pllt, 0, pll);
|
|
|
|
if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
|
|
return round;
|
|
|
|
/*
|
|
* The rate provided by the setting is not an exact match, let's
|
|
* try to improve the result using the fractional parameter
|
|
*/
|
|
frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll);
|
|
|
|
return __pll_params_to_rate(*parent_rate, pllt, frac, pll);
|
|
}
|
|
|
|
static int meson_clk_pll_wait_lock(struct clk_hw *hw)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
int delay = 24000000;
|
|
|
|
do {
|
|
/* Is the clock locked now ? */
|
|
if (meson_parm_read(clk->map, &pll->l))
|
|
return 0;
|
|
|
|
delay--;
|
|
} while (delay > 0);
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static void meson_clk_pll_init(struct clk_hw *hw)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
|
|
if (pll->init_count) {
|
|
meson_parm_write(clk->map, &pll->rst, 1);
|
|
regmap_multi_reg_write(clk->map, pll->init_regs,
|
|
pll->init_count);
|
|
meson_parm_write(clk->map, &pll->rst, 0);
|
|
}
|
|
}
|
|
|
|
static int meson_clk_pll_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
|
|
if (meson_parm_read(clk->map, &pll->rst) ||
|
|
!meson_parm_read(clk->map, &pll->en) ||
|
|
!meson_parm_read(clk->map, &pll->l))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int meson_clk_pll_enable(struct clk_hw *hw)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
|
|
/* do nothing if the PLL is already enabled */
|
|
if (clk_hw_is_enabled(hw))
|
|
return 0;
|
|
|
|
/* Make sure the pll is in reset */
|
|
meson_parm_write(clk->map, &pll->rst, 1);
|
|
|
|
/* Enable the pll */
|
|
meson_parm_write(clk->map, &pll->en, 1);
|
|
|
|
/* Take the pll out reset */
|
|
meson_parm_write(clk->map, &pll->rst, 0);
|
|
|
|
if (meson_clk_pll_wait_lock(hw))
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void meson_clk_pll_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
|
|
/* Put the pll is in reset */
|
|
meson_parm_write(clk->map, &pll->rst, 1);
|
|
|
|
/* Disable the pll */
|
|
meson_parm_write(clk->map, &pll->en, 0);
|
|
}
|
|
|
|
static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_regmap *clk = to_clk_regmap(hw);
|
|
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
|
const struct pll_params_table *pllt;
|
|
unsigned int enabled;
|
|
unsigned long old_rate;
|
|
u16 frac = 0;
|
|
|
|
if (parent_rate == 0 || rate == 0)
|
|
return -EINVAL;
|
|
|
|
old_rate = rate;
|
|
|
|
pllt = meson_clk_get_pll_settings(rate, parent_rate, pll);
|
|
if (!pllt)
|
|
return -EINVAL;
|
|
|
|
enabled = meson_parm_read(clk->map, &pll->en);
|
|
if (enabled)
|
|
meson_clk_pll_disable(hw);
|
|
|
|
meson_parm_write(clk->map, &pll->n, pllt->n);
|
|
meson_parm_write(clk->map, &pll->m, pllt->m);
|
|
|
|
|
|
if (MESON_PARM_APPLICABLE(&pll->frac)) {
|
|
frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);
|
|
meson_parm_write(clk->map, &pll->frac, frac);
|
|
}
|
|
|
|
/* If the pll is stopped, bail out now */
|
|
if (!enabled)
|
|
return 0;
|
|
|
|
if (meson_clk_pll_enable(hw)) {
|
|
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
|
|
__func__, old_rate);
|
|
/*
|
|
* FIXME: Do we really need/want this HACK ?
|
|
* It looks unsafe. what happens if the clock gets into a
|
|
* broken state and we can't lock back on the old_rate ? Looks
|
|
* like an infinite recursion is possible
|
|
*/
|
|
meson_clk_pll_set_rate(hw, old_rate, parent_rate);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct clk_ops meson_clk_pll_ops = {
|
|
.init = meson_clk_pll_init,
|
|
.recalc_rate = meson_clk_pll_recalc_rate,
|
|
.round_rate = meson_clk_pll_round_rate,
|
|
.set_rate = meson_clk_pll_set_rate,
|
|
.is_enabled = meson_clk_pll_is_enabled,
|
|
.enable = meson_clk_pll_enable,
|
|
.disable = meson_clk_pll_disable
|
|
};
|
|
|
|
const struct clk_ops meson_clk_pll_ro_ops = {
|
|
.recalc_rate = meson_clk_pll_recalc_rate,
|
|
.is_enabled = meson_clk_pll_is_enabled,
|
|
};
|