mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 15:20:49 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
185 lines
4.8 KiB
C
185 lines
4.8 KiB
C
/*
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* Private header file for the (dumb) serial driver
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*
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* Copyright (C) 1997 by Theodore Ts'o.
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*
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* Redistribution of this file is permitted under the terms of the GNU
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* Public License (GPL)
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*/
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#ifndef _LINUX_SERIALP_H
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#define _LINUX_SERIALP_H
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/*
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* This is our internal structure for each serial port's state.
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*
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* Many fields are paralleled by the structure used by the serial_struct
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* structure.
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*
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* For definitions of the flags field, see tty.h
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*/
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#include <linux/version.h>
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#include <linux/config.h>
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#include <linux/termios.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/circ_buf.h>
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#include <linux/wait.h>
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struct serial_state {
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int magic;
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int baud_base;
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unsigned long port;
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int irq;
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int flags;
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int hub6;
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int type;
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int line;
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int revision; /* Chip revision (950) */
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int xmit_fifo_size;
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int custom_divisor;
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int count;
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u8 *iomem_base;
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u16 iomem_reg_shift;
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unsigned short close_delay;
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unsigned short closing_wait; /* time to wait before closing */
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struct async_icount icount;
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int io_type;
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struct async_struct *info;
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struct pci_dev *dev;
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};
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struct async_struct {
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int magic;
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unsigned long port;
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int hub6;
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int flags;
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int xmit_fifo_size;
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struct serial_state *state;
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struct tty_struct *tty;
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int read_status_mask;
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int ignore_status_mask;
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int timeout;
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int quot;
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int x_char; /* xon/xoff character */
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int close_delay;
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unsigned short closing_wait;
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unsigned short closing_wait2; /* obsolete */
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int IER; /* Interrupt Enable Register */
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int MCR; /* Modem control register */
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int LCR; /* Line control register */
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int ACR; /* 16950 Additional Control Reg. */
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unsigned long event;
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unsigned long last_active;
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int line;
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int blocked_open; /* # of blocked opens */
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struct circ_buf xmit;
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spinlock_t xmit_lock;
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u8 *iomem_base;
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u16 iomem_reg_shift;
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int io_type;
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struct work_struct work;
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struct tasklet_struct tlet;
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#ifdef DECLARE_WAITQUEUE
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wait_queue_head_t open_wait;
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wait_queue_head_t close_wait;
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wait_queue_head_t delta_msr_wait;
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#else
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struct wait_queue *open_wait;
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struct wait_queue *close_wait;
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struct wait_queue *delta_msr_wait;
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#endif
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struct async_struct *next_port; /* For the linked list */
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struct async_struct *prev_port;
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};
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#define CONFIGURED_SERIAL_PORT(info) ((info)->port || ((info)->iomem_base))
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#define SERIAL_MAGIC 0x5301
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#define SSTATE_MAGIC 0x5302
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/*
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* Events are used to schedule things to happen at timer-interrupt
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* time, instead of at rs interrupt time.
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*/
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#define RS_EVENT_WRITE_WAKEUP 0
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/*
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* Multiport serial configuration structure --- internal structure
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*/
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struct rs_multiport_struct {
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int port1;
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unsigned char mask1, match1;
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int port2;
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unsigned char mask2, match2;
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int port3;
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unsigned char mask3, match3;
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int port4;
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unsigned char mask4, match4;
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int port_monitor;
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};
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#if defined(__alpha__) && !defined(CONFIG_PCI)
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/*
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* Digital did something really horribly wrong with the OUT1 and OUT2
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* lines on at least some ALPHA's. The failure mode is that if either
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* is cleared, the machine locks up with endless interrupts.
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*
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* This is still used by arch/mips/au1000/common/serial.c for some weird
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* reason (mips != alpha!)
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*/
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#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
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#elif defined(CONFIG_SBC8560)
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/*
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* WindRiver did something similarly broken on their SBC8560 board. The
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* UART tristates its IRQ output while OUT2 is clear, but they pulled
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* the interrupt line _up_ instead of down, so if we register the IRQ
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* while the UART is in that state, we die in an IRQ storm. */
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#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
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#else
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#define ALPHA_KLUDGE_MCR 0
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#endif
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/*
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* Definitions for PCI support.
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*/
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#define SPCI_FL_BASE_MASK 0x0007
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#define SPCI_FL_BASE0 0x0000
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#define SPCI_FL_BASE1 0x0001
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#define SPCI_FL_BASE2 0x0002
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#define SPCI_FL_BASE3 0x0003
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#define SPCI_FL_BASE4 0x0004
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#define SPCI_FL_GET_BASE(x) (x & SPCI_FL_BASE_MASK)
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#define SPCI_FL_IRQ_MASK (0x0007 << 4)
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#define SPCI_FL_IRQBASE0 (0x0000 << 4)
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#define SPCI_FL_IRQBASE1 (0x0001 << 4)
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#define SPCI_FL_IRQBASE2 (0x0002 << 4)
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#define SPCI_FL_IRQBASE3 (0x0003 << 4)
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#define SPCI_FL_IRQBASE4 (0x0004 << 4)
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#define SPCI_FL_GET_IRQBASE(x) ((x & SPCI_FL_IRQ_MASK) >> 4)
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/* Use successive BARs (PCI base address registers),
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else use offset into some specified BAR */
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#define SPCI_FL_BASE_TABLE 0x0100
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/* Use successive entries in the irq resource table */
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#define SPCI_FL_IRQ_TABLE 0x0200
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/* Use the irq resource table instead of dev->irq */
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#define SPCI_FL_IRQRESOURCE 0x0400
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/* Use the Base address register size to cap number of ports */
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#define SPCI_FL_REGION_SZ_CAP 0x0800
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/* Do not use irq sharing for this device */
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#define SPCI_FL_NO_SHIRQ 0x1000
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/* This is a PNP device */
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#define SPCI_FL_ISPNP 0x2000
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#define SPCI_FL_PNPDEFAULT (SPCI_FL_IRQRESOURCE|SPCI_FL_ISPNP)
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#endif /* _LINUX_SERIAL_H */
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