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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
482 lines
12 KiB
C
482 lines
12 KiB
C
/*
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* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
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*
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* Licensed under the terms of the GNU GPL License version 2.
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*
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* Library for common functions for Intel SpeedStep v.1 and v.2 support
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*
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <asm/msr.h>
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#include <asm/tsc.h>
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#include "speedstep-lib.h"
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
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"speedstep-lib", msg)
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#define PFX "speedstep-lib: "
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#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
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static int relaxed_check;
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#else
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#define relaxed_check 0
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#endif
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/*********************************************************************
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* GET PROCESSOR CORE SPEED IN KHZ *
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*********************************************************************/
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static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
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{
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/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
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struct {
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unsigned int ratio; /* Frequency Multiplier (x10) */
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u8 bitmap; /* power on configuration bits
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[27, 25:22] (in MSR 0x2a) */
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} msr_decode_mult[] = {
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{ 30, 0x01 },
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{ 35, 0x05 },
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{ 40, 0x02 },
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{ 45, 0x06 },
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{ 50, 0x00 },
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{ 55, 0x04 },
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{ 60, 0x0b },
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{ 65, 0x0f },
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{ 70, 0x09 },
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{ 75, 0x0d },
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{ 80, 0x0a },
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{ 85, 0x26 },
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{ 90, 0x20 },
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{ 100, 0x2b },
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{ 0, 0xff } /* error or unknown value */
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};
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/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
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struct {
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unsigned int value; /* Front Side Bus speed in MHz */
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u8 bitmap; /* power on configuration bits [18: 19]
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(in MSR 0x2a) */
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} msr_decode_fsb[] = {
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{ 66, 0x0 },
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{ 100, 0x2 },
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{ 133, 0x1 },
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{ 0, 0xff}
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};
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u32 msr_lo, msr_tmp;
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int i = 0, j = 0;
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/* read MSR 0x2a - we only need the low 32 bits */
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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msr_tmp = msr_lo;
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/* decode the FSB */
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msr_tmp &= 0x00c0000;
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msr_tmp >>= 18;
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while (msr_tmp != msr_decode_fsb[i].bitmap) {
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if (msr_decode_fsb[i].bitmap == 0xff)
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return 0;
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i++;
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}
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/* decode the multiplier */
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if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
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dprintk("workaround for early PIIIs\n");
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msr_lo &= 0x03c00000;
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} else
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msr_lo &= 0x0bc00000;
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msr_lo >>= 22;
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while (msr_lo != msr_decode_mult[j].bitmap) {
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if (msr_decode_mult[j].bitmap == 0xff)
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return 0;
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j++;
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}
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dprintk("speed is %u\n",
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(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
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return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
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}
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static unsigned int pentiumM_get_frequency(void)
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{
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u32 msr_lo, msr_tmp;
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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/* see table B-2 of 24547212.pdf */
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if (msr_lo & 0x00040000) {
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printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
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msr_lo, msr_tmp);
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return 0;
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}
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msr_tmp = (msr_lo >> 22) & 0x1f;
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dprintk("bits 22-26 are 0x%x, speed is %u\n",
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msr_tmp, (msr_tmp * 100 * 1000));
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return msr_tmp * 100 * 1000;
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}
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static unsigned int pentium_core_get_frequency(void)
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{
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u32 fsb = 0;
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u32 msr_lo, msr_tmp;
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int ret;
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rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
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/* see table B-2 of 25366920.pdf */
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switch (msr_lo & 0x07) {
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case 5:
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fsb = 100000;
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break;
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case 1:
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fsb = 133333;
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break;
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case 3:
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fsb = 166667;
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break;
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case 2:
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fsb = 200000;
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break;
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case 0:
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fsb = 266667;
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break;
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case 4:
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fsb = 333333;
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break;
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default:
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printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
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}
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
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msr_lo, msr_tmp);
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msr_tmp = (msr_lo >> 22) & 0x1f;
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dprintk("bits 22-26 are 0x%x, speed is %u\n",
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msr_tmp, (msr_tmp * fsb));
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ret = (msr_tmp * fsb);
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return ret;
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}
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static unsigned int pentium4_get_frequency(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u32 msr_lo, msr_hi, mult;
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unsigned int fsb = 0;
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unsigned int ret;
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u8 fsb_code;
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/* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
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* to System Bus Frequency Ratio Field in the Processor Frequency
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* Configuration Register of the MSR. Therefore the current
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* frequency cannot be calculated and has to be measured.
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*/
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if (c->x86_model < 2)
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return cpu_khz;
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rdmsr(0x2c, msr_lo, msr_hi);
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dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
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/* decode the FSB: see IA-32 Intel (C) Architecture Software
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* Developer's Manual, Volume 3: System Prgramming Guide,
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* revision #12 in Table B-1: MSRs in the Pentium 4 and
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* Intel Xeon Processors, on page B-4 and B-5.
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*/
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fsb_code = (msr_lo >> 16) & 0x7;
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switch (fsb_code) {
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case 0:
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fsb = 100 * 1000;
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break;
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case 1:
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fsb = 13333 * 10;
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break;
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case 2:
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fsb = 200 * 1000;
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break;
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}
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if (!fsb)
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printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
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"Please send an e-mail to <linux@brodo.de>\n");
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/* Multiplier. */
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mult = msr_lo >> 24;
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dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
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fsb, mult, (fsb * mult));
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ret = (fsb * mult);
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return ret;
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}
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/* Warning: may get called from smp_call_function_single. */
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unsigned int speedstep_get_frequency(enum speedstep_processor processor)
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{
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switch (processor) {
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case SPEEDSTEP_CPU_PCORE:
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return pentium_core_get_frequency();
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case SPEEDSTEP_CPU_PM:
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return pentiumM_get_frequency();
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case SPEEDSTEP_CPU_P4D:
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case SPEEDSTEP_CPU_P4M:
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return pentium4_get_frequency();
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case SPEEDSTEP_CPU_PIII_T:
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case SPEEDSTEP_CPU_PIII_C:
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case SPEEDSTEP_CPU_PIII_C_EARLY:
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return pentium3_get_frequency(processor);
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default:
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return 0;
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};
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return 0;
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}
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EXPORT_SYMBOL_GPL(speedstep_get_frequency);
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/*********************************************************************
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* DETECT SPEEDSTEP-CAPABLE PROCESSOR *
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*********************************************************************/
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unsigned int speedstep_detect_processor(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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u32 ebx, msr_lo, msr_hi;
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dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
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if ((c->x86_vendor != X86_VENDOR_INTEL) ||
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((c->x86 != 6) && (c->x86 != 0xF)))
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return 0;
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if (c->x86 == 0xF) {
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/* Intel Mobile Pentium 4-M
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* or Intel Mobile Pentium 4 with 533 MHz FSB */
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if (c->x86_model != 2)
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return 0;
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ebx = cpuid_ebx(0x00000001);
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ebx &= 0x000000FF;
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dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
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switch (c->x86_mask) {
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case 4:
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/*
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* B-stepping [M-P4-M]
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* sample has ebx = 0x0f, production has 0x0e.
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*/
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if ((ebx == 0x0e) || (ebx == 0x0f))
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return SPEEDSTEP_CPU_P4M;
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break;
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case 7:
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/*
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* C-stepping [M-P4-M]
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* needs to have ebx=0x0e, else it's a celeron:
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* cf. 25130917.pdf / page 7, footnote 5 even
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* though 25072120.pdf / page 7 doesn't say
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* samples are only of B-stepping...
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*/
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if (ebx == 0x0e)
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return SPEEDSTEP_CPU_P4M;
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break;
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case 9:
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/*
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* D-stepping [M-P4-M or M-P4/533]
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*
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* this is totally strange: CPUID 0x0F29 is
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* used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
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* The latter need to be sorted out as they don't
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* support speedstep.
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* Celerons with CPUID 0x0F29 may have either
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* ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
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* specific.
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* M-P4-Ms may have either ebx=0xe or 0xf [see above]
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* M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
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* also, M-P4M HTs have ebx=0x8, too
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* For now, they are distinguished by the model_id
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* string
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*/
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if ((ebx == 0x0e) ||
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(strstr(c->x86_model_id,
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"Mobile Intel(R) Pentium(R) 4") != NULL))
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return SPEEDSTEP_CPU_P4M;
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break;
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default:
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break;
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}
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return 0;
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}
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switch (c->x86_model) {
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case 0x0B: /* Intel PIII [Tualatin] */
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/* cpuid_ebx(1) is 0x04 for desktop PIII,
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* 0x06 for mobile PIII-M */
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ebx = cpuid_ebx(0x00000001);
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dprintk("ebx is %x\n", ebx);
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ebx &= 0x000000FF;
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if (ebx != 0x06)
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return 0;
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/* So far all PIII-M processors support SpeedStep. See
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* Intel's 24540640.pdf of June 2003
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*/
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return SPEEDSTEP_CPU_PIII_T;
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case 0x08: /* Intel PIII [Coppermine] */
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/* all mobile PIII Coppermines have FSB 100 MHz
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* ==> sort out a few desktop PIIIs. */
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
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dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
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msr_lo, msr_hi);
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msr_lo &= 0x00c0000;
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if (msr_lo != 0x0080000)
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return 0;
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/*
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* If the processor is a mobile version,
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* platform ID has bit 50 set
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* it has SpeedStep technology if either
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* bit 56 or 57 is set
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*/
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rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
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dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
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msr_lo, msr_hi);
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if ((msr_hi & (1<<18)) &&
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(relaxed_check ? 1 : (msr_hi & (3<<24)))) {
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if (c->x86_mask == 0x01) {
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dprintk("early PIII version\n");
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return SPEEDSTEP_CPU_PIII_C_EARLY;
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} else
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return SPEEDSTEP_CPU_PIII_C;
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}
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default:
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return 0;
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}
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}
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EXPORT_SYMBOL_GPL(speedstep_detect_processor);
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/*********************************************************************
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* DETECT SPEEDSTEP SPEEDS *
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*********************************************************************/
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unsigned int speedstep_get_freqs(enum speedstep_processor processor,
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unsigned int *low_speed,
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unsigned int *high_speed,
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unsigned int *transition_latency,
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void (*set_state) (unsigned int state))
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{
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unsigned int prev_speed;
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unsigned int ret = 0;
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unsigned long flags;
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struct timeval tv1, tv2;
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if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
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return -EINVAL;
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dprintk("trying to determine both speeds\n");
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/* get current speed */
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prev_speed = speedstep_get_frequency(processor);
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if (!prev_speed)
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return -EIO;
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dprintk("previous speed is %u\n", prev_speed);
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local_irq_save(flags);
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/* switch to low state */
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set_state(SPEEDSTEP_LOW);
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*low_speed = speedstep_get_frequency(processor);
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if (!*low_speed) {
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ret = -EIO;
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goto out;
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}
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dprintk("low speed is %u\n", *low_speed);
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/* start latency measurement */
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if (transition_latency)
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do_gettimeofday(&tv1);
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/* switch to high state */
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set_state(SPEEDSTEP_HIGH);
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/* end latency measurement */
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if (transition_latency)
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do_gettimeofday(&tv2);
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*high_speed = speedstep_get_frequency(processor);
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if (!*high_speed) {
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ret = -EIO;
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goto out;
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}
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dprintk("high speed is %u\n", *high_speed);
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if (*low_speed == *high_speed) {
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ret = -ENODEV;
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goto out;
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}
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/* switch to previous state, if necessary */
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if (*high_speed != prev_speed)
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set_state(SPEEDSTEP_LOW);
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if (transition_latency) {
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*transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
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tv2.tv_usec - tv1.tv_usec;
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dprintk("transition latency is %u uSec\n", *transition_latency);
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/* convert uSec to nSec and add 20% for safety reasons */
|
|
*transition_latency *= 1200;
|
|
|
|
/* check if the latency measurement is too high or too low
|
|
* and set it to a safe value (500uSec) in that case
|
|
*/
|
|
if (*transition_latency > 10000000 ||
|
|
*transition_latency < 50000) {
|
|
printk(KERN_WARNING PFX "frequency transition "
|
|
"measured seems out of range (%u "
|
|
"nSec), falling back to a safe one of"
|
|
"%u nSec.\n",
|
|
*transition_latency, 500000);
|
|
*transition_latency = 500000;
|
|
}
|
|
}
|
|
|
|
out:
|
|
local_irq_restore(flags);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(speedstep_get_freqs);
|
|
|
|
#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
|
|
module_param(relaxed_check, int, 0444);
|
|
MODULE_PARM_DESC(relaxed_check,
|
|
"Don't do all checks for speedstep capability.");
|
|
#endif
|
|
|
|
MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
|
|
MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
|
|
MODULE_LICENSE("GPL");
|