mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 04:46:32 +07:00
2e8566106d
- A couple of fixes on imx7d-pico and imx7d-nitrogen7 boards to correct
the description of the Wifi clock.
- Change SW2ISO count to get a safer ARM LDO ramp-up time, so that
different boards can be covered. This fixes the ARM LDO failure seen
on some customer boards.
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Merge tag 'imx-fixes-4.20-3' into imx7d/pico
i.MX fixes for 4.20, round 3:
- A couple of fixes on imx7d-pico and imx7d-nitrogen7 boards to correct
the description of the Wifi clock.
- Change SW2ISO count to get a safer ARM LDO ramp-up time, so that
different boards can be covered. This fixes the ARM LDO failure seen
on some customer boards.
696 lines
16 KiB
Plaintext
696 lines
16 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR X11
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/*
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* Copyright 2016 Boundary Devices, Inc.
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*/
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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model = "Boundary Devices i.MX7 Nitrogen7 Board";
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compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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backlight-j9 {
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compatible = "gpio-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_backlight_j9>;
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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default-on;
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};
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backlight_lcd: backlight-j20 {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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panel-lcd {
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compatible = "okaya,rs800480t-7x0gp";
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backlight = <&backlight_lcd>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&lcdif_out>;
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};
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};
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_can2_3v3: regulator-can2-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "can2-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
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};
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reg_vref_1v8: regulator-vref-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vref-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_vref_3v3: regulator-vref-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vref-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_wlan: regulator-wlan {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "reg_wlan";
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startup-delay-us = <70000>;
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gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
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clock-names = "ext_clock";
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&adc2 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
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<&clks IMX7D_CLKO2_ROOT_DIV>;
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assigned-clock-parents = <&clks IMX7D_CKIL>;
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assigned-clock-rates = <0>, <32768>;
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};
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&cpu0 {
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cpu-supply = <&sw1a_reg>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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reg = <4>;
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};
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};
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can2_3v3>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze3000@8 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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rtc@68 {
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compatible = "microcrystal,rv4162";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_rv4162>;
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reg = <0x68>;
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interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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touch@48 {
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compatible = "ti,tsc2004";
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reg = <0x48>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
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interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
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wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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codec: wm8960@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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clock-names = "mclk";
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wlf,shared-lrclk;
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};
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};
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&lcdif {
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status = "okay";
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port {
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lcdif_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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status = "okay";
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};
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&uart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6>;
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assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg2>;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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vmmc-supply = <&vgen3_reg>;
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bus-width = <4>;
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fsl,tuning-step = <2>;
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wakeup-source;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <4>;
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non-removable;
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vmmc-supply = <®_wlan>;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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cap-power-off-card;
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keep-power-in-suspend;
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status = "okay";
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wlcore: wlcore@2 {
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compatible = "ti,wl1271";
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reg = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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ref-clock-frequency = <38400000>;
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};
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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fsl,tuning-step = <2>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d
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MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
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MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
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MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
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MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d
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MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d
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MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
|
|
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_rv4162: i2c2-rv4162grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
|
|
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79
|
|
MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
|
|
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_j2: j2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d
|
|
MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d
|
|
MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d
|
|
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d
|
|
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d
|
|
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d
|
|
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d
|
|
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d
|
|
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d
|
|
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d
|
|
MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d
|
|
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d
|
|
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d
|
|
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d
|
|
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d
|
|
MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d
|
|
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d
|
|
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d
|
|
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d
|
|
MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d
|
|
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d
|
|
MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d
|
|
MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d
|
|
MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d
|
|
MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d
|
|
MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d
|
|
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d
|
|
MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d
|
|
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d
|
|
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d
|
|
MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d
|
|
MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d
|
|
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d
|
|
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_dat: lcdifdatgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
|
|
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
|
|
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
|
|
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
|
|
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
|
|
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
|
|
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
|
|
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
|
|
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
|
|
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
|
|
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
|
|
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
|
|
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
|
|
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
|
|
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
|
|
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
|
|
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
|
|
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
|
|
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
|
|
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
|
|
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
|
|
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
|
|
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
|
|
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
|
|
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
|
|
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
|
|
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
|
|
MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
|
|
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
|
|
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart6: uart6grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
|
|
MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
|
|
MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
|
|
MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg2: usbotg2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d
|
|
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
|
MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59
|
|
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
>;
|
|
};
|
|
};
|
|
|
|
&iomuxc_lpsr {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_hog_2>;
|
|
|
|
pinctrl_hog_2: hoggrp-2 {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d
|
|
MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_backlight_j9: backlightj9grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg1: usbotg1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x7d
|
|
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog1: wdog1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x75
|
|
>;
|
|
};
|
|
};
|