mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
9fb1e350e1
Updates the ucc_geth device driver to check the new rx-clock-name and tx-clock-name properties first. If present, it uses the new function qe_clock_source() to obtain the clock source. Otherwise, it checks the deprecated rx-clock and tx-clock properties. Update the device trees for 832x, 836x, and 8568 to contain the new property names only. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
380 lines
8.4 KiB
Plaintext
380 lines
8.4 KiB
Plaintext
/*
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* MPC8360E EMDS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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/memreserve/ 00000000 1000000;
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*/
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/ {
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model = "MPC8360MDS";
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compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8360@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <3EF1480>;
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bus-frequency = <FBC5200>;
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clock-frequency = <1F78A400>;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 10000000>;
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};
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bcsr@f8000000 {
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device_type = "board-control";
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reg = <f8000000 8000>;
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};
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soc8360@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <FBC5200>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <68>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <3100 100>;
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interrupts = <f 8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <FBC5200>;
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interrupts = <9 8>;
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interrupt-parent = < &ipic >;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <FBC5200>;
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interrupts = <a 8>;
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interrupt-parent = < &ipic >;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 10000>;
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interrupts = <b 8>;
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interrupt-parent = < &ipic >;
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num-channels = <4>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000007e>;
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/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
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descriptor-types-mask = <01010ebf>;
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};
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <700 100>;
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device_type = "ipic";
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};
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par_io@1400 {
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reg = <1400 100>;
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device_type = "par_io";
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num-ports = <7>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 3 1 0 1 0 /* TxD0 */
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0 4 1 0 1 0 /* TxD1 */
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0 5 1 0 1 0 /* TxD2 */
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0 6 1 0 1 0 /* TxD3 */
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1 6 1 0 3 0 /* TxD4 */
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1 7 1 0 1 0 /* TxD5 */
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1 9 1 0 2 0 /* TxD6 */
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1 a 1 0 2 0 /* TxD7 */
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0 9 2 0 1 0 /* RxD0 */
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0 a 2 0 1 0 /* RxD1 */
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0 b 2 0 1 0 /* RxD2 */
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0 c 2 0 1 0 /* RxD3 */
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0 d 2 0 1 0 /* RxD4 */
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1 1 2 0 2 0 /* RxD5 */
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1 0 2 0 2 0 /* RxD6 */
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1 4 2 0 2 0 /* RxD7 */
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0 7 1 0 1 0 /* TX_EN */
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0 8 1 0 1 0 /* TX_ER */
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0 f 2 0 1 0 /* RX_DV */
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0 10 2 0 1 0 /* RX_ER */
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0 0 2 0 1 0 /* RX_CLK */
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2 9 1 0 3 0 /* GTX_CLK - CLK10 */
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2 8 2 0 1 0>; /* GTX125 - CLK9 */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 11 1 0 1 0 /* TxD0 */
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0 12 1 0 1 0 /* TxD1 */
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0 13 1 0 1 0 /* TxD2 */
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0 14 1 0 1 0 /* TxD3 */
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1 2 1 0 1 0 /* TxD4 */
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1 3 1 0 2 0 /* TxD5 */
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1 5 1 0 3 0 /* TxD6 */
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1 8 1 0 3 0 /* TxD7 */
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0 17 2 0 1 0 /* RxD0 */
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0 18 2 0 1 0 /* RxD1 */
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0 19 2 0 1 0 /* RxD2 */
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0 1a 2 0 1 0 /* RxD3 */
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0 1b 2 0 1 0 /* RxD4 */
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1 c 2 0 2 0 /* RxD5 */
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1 d 2 0 3 0 /* RxD6 */
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1 b 2 0 2 0 /* RxD7 */
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0 15 1 0 1 0 /* TX_EN */
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0 16 1 0 1 0 /* TX_ER */
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0 1d 2 0 1 0 /* RX_DV */
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0 1e 2 0 1 0 /* RX_ER */
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0 1f 2 0 1 0 /* RX_CLK */
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2 2 1 0 2 0 /* GTX_CLK - CLK10 */
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2 3 2 0 1 0 /* GTX125 - CLK4 */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0>; /* MDC */
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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model = "QE";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <179A7B00>;
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muram@10000 {
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device_type = "muram";
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ranges = <0 00010000 0000c000>;
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data-only@0{
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reg = <0 c000>;
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};
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};
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spi@4c0 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <4c0 40>;
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interrupts = <2>;
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interrupt-parent = < &qeic >;
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mode = "cpu";
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};
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spi@500 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <500 40>;
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interrupts = <1>;
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interrupt-parent = < &qeic >;
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mode = "cpu";
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};
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usb@6c0 {
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device_type = "usb";
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compatible = "qe_udc";
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reg = <6c0 40 8B00 100>;
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interrupts = <b>;
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interrupt-parent = < &qeic >;
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mode = "slave";
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};
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enet0: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <1>;
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device-id = <1>;
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reg = <2000 200>;
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interrupts = <20>;
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interrupt-parent = < &qeic >;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk9";
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phy-handle = < &phy0 >;
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phy-connection-type = "rgmii-id";
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pio-handle = < &pio1 >;
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};
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enet1: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <2>;
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device-id = <2>;
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reg = <3000 200>;
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interrupts = <21>;
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interrupt-parent = < &qeic >;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk4";
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phy-handle = < &phy1 >;
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phy-connection-type = "rgmii-id";
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pio-handle = < &pio2 >;
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};
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2120 18>;
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device_type = "mdio";
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compatible = "ucc_geth_phy";
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phy0: ethernet-phy@00 {
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interrupt-parent = < &ipic >;
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interrupts = <11 8>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@01 {
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interrupt-parent = < &ipic >;
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interrupts = <12 8>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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};
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qeic: qeic@80 {
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interrupt-controller;
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device_type = "qeic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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big-endian;
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interrupts = <20 8 21 8>; //high:32 low:33
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interrupt-parent = < &ipic >;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 AD17 */
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8800 0 0 1 &ipic 14 8
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8800 0 0 2 &ipic 15 8
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8800 0 0 3 &ipic 16 8
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8800 0 0 4 &ipic 17 8
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/* IDSEL 0x12 AD18 */
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9000 0 0 1 &ipic 16 8
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9000 0 0 2 &ipic 17 8
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9000 0 0 3 &ipic 14 8
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9000 0 0 4 &ipic 15 8
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/* IDSEL 0x13 AD19 */
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9800 0 0 1 &ipic 17 8
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9800 0 0 2 &ipic 14 8
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9800 0 0 3 &ipic 15 8
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9800 0 0 4 &ipic 16 8
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/* IDSEL 0x15 AD21*/
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a800 0 0 1 &ipic 14 8
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a800 0 0 2 &ipic 15 8
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a800 0 0 3 &ipic 16 8
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a800 0 0 4 &ipic 17 8
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/* IDSEL 0x16 AD22*/
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b000 0 0 1 &ipic 17 8
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b000 0 0 2 &ipic 14 8
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b000 0 0 3 &ipic 15 8
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b000 0 0 4 &ipic 16 8
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/* IDSEL 0x17 AD23*/
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b800 0 0 1 &ipic 16 8
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b800 0 0 2 &ipic 17 8
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b800 0 0 3 &ipic 14 8
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b800 0 0 4 &ipic 15 8
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/* IDSEL 0x18 AD24*/
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c000 0 0 1 &ipic 15 8
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c000 0 0 2 &ipic 16 8
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c000 0 0 3 &ipic 17 8
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c000 0 0 4 &ipic 14 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 a0000000 a0000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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