mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 12:16:45 +07:00
8a8b6eb7a8
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static? drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static? drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type? drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921) The last one looks like a real bug because we don't return an error on allocation failure. Cc: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
984 lines
24 KiB
C
984 lines
24 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/string.h>
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#define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
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#define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
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#define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
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#define ADPLL_PWRCTRL_OFFSET 0x00
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#define ADPLL_PWRCTRL_PONIN 5
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#define ADPLL_PWRCTRL_PGOODIN 4
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#define ADPLL_PWRCTRL_RET 3
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#define ADPLL_PWRCTRL_ISORET 2
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#define ADPLL_PWRCTRL_ISOSCAN 1
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#define ADPLL_PWRCTRL_OFFMODE 0
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#define ADPLL_CLKCTRL_OFFSET 0x04
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#define ADPLL_CLKCTRL_CLKDCOLDOEN 29
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#define ADPLL_CLKCTRL_IDLE 23
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#define ADPLL_CLKCTRL_CLKOUTEN 20
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#define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
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#define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
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#define ADPLL_CLKCTRL_ULOWCLKEN 18
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#define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
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#define ADPLL_CLKCTRL_M2PWDNZ 16
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#define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
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#define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
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#define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
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#define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
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#define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
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#define ADPLL_CLKCTRL_TINITZ 0
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#define ADPLL_TENABLE_OFFSET 0x08
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#define ADPLL_TENABLEDIV_OFFSET 0x8c
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#define ADPLL_M2NDIV_OFFSET 0x10
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#define ADPLL_M2NDIV_M2 16
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#define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
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#define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
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#define ADPLL_MN2DIV_OFFSET 0x14
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#define ADPLL_MN2DIV_N2 16
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#define ADPLL_FRACDIV_OFFSET 0x18
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#define ADPLL_FRACDIV_REGSD 24
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#define ADPLL_FRACDIV_FRACTIONALM 0
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#define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
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#define ADPLL_BWCTRL_OFFSET 0x1c
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#define ADPLL_BWCTRL_BWCONTROL 1
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#define ADPLL_BWCTRL_BW_INCR_DECRZ 0
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#define ADPLL_RESERVED_OFFSET 0x20
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#define ADPLL_STATUS_OFFSET 0x24
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#define ADPLL_STATUS_PONOUT 31
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#define ADPLL_STATUS_PGOODOUT 30
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#define ADPLL_STATUS_LDOPWDN 29
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#define ADPLL_STATUS_RECAL_BSTATUS3 28
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#define ADPLL_STATUS_RECAL_OPPIN 27
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#define ADPLL_STATUS_PHASELOCK 10
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#define ADPLL_STATUS_FREQLOCK 9
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#define ADPLL_STATUS_BYPASSACK 8
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#define ADPLL_STATUS_LOSSREF 6
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#define ADPLL_STATUS_CLKOUTENACK 5
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#define ADPLL_STATUS_LOCK2 4
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#define ADPLL_STATUS_M2CHANGEACK 3
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#define ADPLL_STATUS_HIGHJITTER 1
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#define ADPLL_STATUS_BYPASS 0
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#define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
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BIT(ADPLL_STATUS_FREQLOCK))
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#define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
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#define ADPLL_M3DIV_M3 0
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#define ADPLL_M3DIV_M3_WIDTH 5
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#define ADPLL_M3DIV_M3_MASK 0x1f
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#define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
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#define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
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#define ADPLL_RAMPCTRL_CLKRAMPRATE 16
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#define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
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#define MAX_ADPLL_INPUTS 3
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#define MAX_ADPLL_OUTPUTS 4
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#define ADPLL_MAX_RETRIES 5
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#define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
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#define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
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#define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
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enum ti_adpll_clocks {
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TI_ADPLL_DCO,
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TI_ADPLL_DCO_GATE,
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TI_ADPLL_N2,
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TI_ADPLL_M2,
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TI_ADPLL_M2_GATE,
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TI_ADPLL_BYPASS,
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TI_ADPLL_HIF,
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TI_ADPLL_DIV2,
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TI_ADPLL_CLKOUT,
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TI_ADPLL_CLKOUT2,
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TI_ADPLL_M3,
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};
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#define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
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enum ti_adpll_inputs {
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TI_ADPLL_CLKINP,
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TI_ADPLL_CLKINPULOW,
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TI_ADPLL_CLKINPHIF,
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};
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enum ti_adpll_s_outputs {
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TI_ADPLL_S_DCOCLKLDO,
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TI_ADPLL_S_CLKOUT,
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TI_ADPLL_S_CLKOUTX2,
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TI_ADPLL_S_CLKOUTHIF,
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};
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enum ti_adpll_lj_outputs {
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TI_ADPLL_LJ_CLKDCOLDO,
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TI_ADPLL_LJ_CLKOUT,
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TI_ADPLL_LJ_CLKOUTLDO,
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};
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struct ti_adpll_platform_data {
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const bool is_type_s;
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const int nr_max_inputs;
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const int nr_max_outputs;
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const int output_index;
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};
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struct ti_adpll_clock {
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struct clk *clk;
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struct clk_lookup *cl;
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void (*unregister)(struct clk *clk);
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};
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struct ti_adpll_dco_data {
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struct clk_hw hw;
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};
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struct ti_adpll_clkout_data {
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struct ti_adpll_data *adpll;
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struct clk_gate gate;
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struct clk_hw hw;
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};
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struct ti_adpll_data {
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struct device *dev;
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const struct ti_adpll_platform_data *c;
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struct device_node *np;
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unsigned long pa;
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void __iomem *iobase;
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void __iomem *regs;
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spinlock_t lock; /* For ADPLL shared register access */
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const char *parent_names[MAX_ADPLL_INPUTS];
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struct clk *parent_clocks[MAX_ADPLL_INPUTS];
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struct ti_adpll_clock *clocks;
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struct clk_onecell_data outputs;
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struct ti_adpll_dco_data dco;
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};
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static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
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int output_index,
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const char *postfix)
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{
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const char *name;
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int err;
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if (output_index >= 0) {
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err = of_property_read_string_index(d->np,
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"clock-output-names",
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output_index,
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&name);
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if (err)
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return NULL;
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} else {
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const char *base_name = "adpll";
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char *buf;
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buf = devm_kzalloc(d->dev, 8 + 1 + strlen(base_name) + 1 +
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strlen(postfix), GFP_KERNEL);
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if (!buf)
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return NULL;
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sprintf(buf, "%08lx.%s.%s", d->pa, base_name, postfix);
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name = buf;
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}
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return name;
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}
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#define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
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static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
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int index, int output_index, const char *name,
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void (*unregister)(struct clk *clk))
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{
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struct clk_lookup *cl;
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const char *postfix = NULL;
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char con_id[ADPLL_MAX_CON_ID];
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d->clocks[index].clk = clock;
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d->clocks[index].unregister = unregister;
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/* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
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postfix = strrchr(name, '.');
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if (strlen(postfix) > 1) {
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if (strlen(postfix) > ADPLL_MAX_CON_ID)
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dev_warn(d->dev, "clock %s con_id lookup may fail\n",
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name);
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snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
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cl = clkdev_create(clock, con_id, NULL);
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if (!cl)
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return -ENOMEM;
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d->clocks[index].cl = cl;
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} else {
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dev_warn(d->dev, "no con_id for clock %s\n", name);
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}
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if (output_index < 0)
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return 0;
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d->outputs.clks[output_index] = clock;
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d->outputs.clk_num++;
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return 0;
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}
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static int ti_adpll_init_divider(struct ti_adpll_data *d,
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enum ti_adpll_clocks index,
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int output_index, char *name,
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struct clk *parent_clock,
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void __iomem *reg,
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u8 shift, u8 width,
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u8 clk_divider_flags)
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{
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const char *child_name;
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const char *parent_name;
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struct clk *clock;
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child_name = ti_adpll_clk_get_name(d, output_index, name);
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if (!child_name)
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return -EINVAL;
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parent_name = __clk_get_name(parent_clock);
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clock = clk_register_divider(d->dev, child_name, parent_name, 0,
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reg, shift, width, clk_divider_flags,
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&d->lock);
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if (IS_ERR(clock)) {
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dev_err(d->dev, "failed to register divider %s: %li\n",
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name, PTR_ERR(clock));
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return PTR_ERR(clock);
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}
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return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
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clk_unregister_divider);
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}
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static int ti_adpll_init_mux(struct ti_adpll_data *d,
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enum ti_adpll_clocks index,
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char *name, struct clk *clk0,
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struct clk *clk1,
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void __iomem *reg,
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u8 shift)
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{
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const char *child_name;
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const char *parents[2];
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struct clk *clock;
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child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
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if (!child_name)
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return -ENOMEM;
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parents[0] = __clk_get_name(clk0);
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parents[1] = __clk_get_name(clk1);
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clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
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reg, shift, 1, 0, &d->lock);
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if (IS_ERR(clock)) {
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dev_err(d->dev, "failed to register mux %s: %li\n",
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name, PTR_ERR(clock));
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return PTR_ERR(clock);
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}
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return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
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clk_unregister_mux);
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}
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static int ti_adpll_init_gate(struct ti_adpll_data *d,
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enum ti_adpll_clocks index,
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int output_index, char *name,
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struct clk *parent_clock,
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void __iomem *reg,
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u8 bit_idx,
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u8 clk_gate_flags)
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{
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const char *child_name;
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const char *parent_name;
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struct clk *clock;
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child_name = ti_adpll_clk_get_name(d, output_index, name);
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if (!child_name)
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return -EINVAL;
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parent_name = __clk_get_name(parent_clock);
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clock = clk_register_gate(d->dev, child_name, parent_name, 0,
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reg, bit_idx, clk_gate_flags,
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&d->lock);
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if (IS_ERR(clock)) {
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dev_err(d->dev, "failed to register gate %s: %li\n",
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name, PTR_ERR(clock));
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return PTR_ERR(clock);
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}
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return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
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clk_unregister_gate);
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}
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static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
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enum ti_adpll_clocks index,
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char *name,
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struct clk *parent_clock,
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unsigned int mult,
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unsigned int div)
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{
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const char *child_name;
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const char *parent_name;
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struct clk *clock;
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child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
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if (!child_name)
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return -ENOMEM;
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parent_name = __clk_get_name(parent_clock);
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clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
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0, mult, div);
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if (IS_ERR(clock))
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return PTR_ERR(clock);
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return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
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clk_unregister);
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}
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static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
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{
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unsigned long flags;
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u32 v;
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spin_lock_irqsave(&d->lock, flags);
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v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
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v |= BIT(ADPLL_CLKCTRL_IDLE);
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writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
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spin_unlock_irqrestore(&d->lock, flags);
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}
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static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
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{
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unsigned long flags;
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u32 v;
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spin_lock_irqsave(&d->lock, flags);
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v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
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v &= ~BIT(ADPLL_CLKCTRL_IDLE);
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writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
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spin_unlock_irqrestore(&d->lock, flags);
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}
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static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
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{
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u32 v;
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v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
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return v & BIT(ADPLL_STATUS_BYPASS);
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}
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/*
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* Locked and bypass are not actually mutually exclusive: if you only care
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* about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
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* the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
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*/
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static bool ti_adpll_is_locked(struct ti_adpll_data *d)
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{
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u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
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return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
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}
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static int ti_adpll_wait_lock(struct ti_adpll_data *d)
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{
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int retries = ADPLL_MAX_RETRIES;
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do {
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if (ti_adpll_is_locked(d))
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return 0;
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usleep_range(200, 300);
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} while (retries--);
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dev_err(d->dev, "pll failed to lock\n");
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return -ETIMEDOUT;
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}
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static int ti_adpll_prepare(struct clk_hw *hw)
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{
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struct ti_adpll_dco_data *dco = to_dco(hw);
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struct ti_adpll_data *d = to_adpll(dco);
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ti_adpll_clear_idle_bypass(d);
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ti_adpll_wait_lock(d);
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return 0;
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}
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static void ti_adpll_unprepare(struct clk_hw *hw)
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{
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struct ti_adpll_dco_data *dco = to_dco(hw);
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struct ti_adpll_data *d = to_adpll(dco);
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ti_adpll_set_idle_bypass(d);
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}
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static int ti_adpll_is_prepared(struct clk_hw *hw)
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{
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struct ti_adpll_dco_data *dco = to_dco(hw);
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struct ti_adpll_data *d = to_adpll(dco);
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return ti_adpll_is_locked(d);
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}
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/*
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* Note that the DCO clock is never subject to bypass: if the PLL is off,
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* dcoclk is low.
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*/
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static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ti_adpll_dco_data *dco = to_dco(hw);
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struct ti_adpll_data *d = to_adpll(dco);
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u32 frac_m, divider, v;
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u64 rate;
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unsigned long flags;
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if (ti_adpll_clock_is_bypass(d))
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return 0;
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spin_lock_irqsave(&d->lock, flags);
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frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
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frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
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rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
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rate += frac_m;
|
|
rate *= parent_rate;
|
|
divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
|
|
spin_unlock_irqrestore(&d->lock, flags);
|
|
|
|
do_div(rate, divider);
|
|
|
|
if (d->c->is_type_s) {
|
|
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
|
|
if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
|
|
rate *= 4;
|
|
rate *= 2;
|
|
}
|
|
|
|
return rate;
|
|
}
|
|
|
|
/* PLL parent is always clkinp, bypass only affects the children */
|
|
static u8 ti_adpll_get_parent(struct clk_hw *hw)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops ti_adpll_ops = {
|
|
.prepare = ti_adpll_prepare,
|
|
.unprepare = ti_adpll_unprepare,
|
|
.is_prepared = ti_adpll_is_prepared,
|
|
.recalc_rate = ti_adpll_recalc_rate,
|
|
.get_parent = ti_adpll_get_parent,
|
|
};
|
|
|
|
static int ti_adpll_init_dco(struct ti_adpll_data *d)
|
|
{
|
|
struct clk_init_data init;
|
|
struct clk *clock;
|
|
const char *postfix;
|
|
int width, err;
|
|
|
|
d->outputs.clks = devm_kzalloc(d->dev, sizeof(struct clk *) *
|
|
MAX_ADPLL_OUTPUTS,
|
|
GFP_KERNEL);
|
|
if (!d->outputs.clks)
|
|
return -ENOMEM;
|
|
|
|
if (d->c->output_index < 0)
|
|
postfix = "dco";
|
|
else
|
|
postfix = NULL;
|
|
|
|
init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
|
|
if (!init.name)
|
|
return -EINVAL;
|
|
|
|
init.parent_names = d->parent_names;
|
|
init.num_parents = d->c->nr_max_inputs;
|
|
init.ops = &ti_adpll_ops;
|
|
init.flags = CLK_GET_RATE_NOCACHE;
|
|
d->dco.hw.init = &init;
|
|
|
|
if (d->c->is_type_s)
|
|
width = 5;
|
|
else
|
|
width = 4;
|
|
|
|
/* Internal input clock divider N2 */
|
|
err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
|
|
d->parent_clocks[TI_ADPLL_CLKINP],
|
|
d->regs + ADPLL_MN2DIV_OFFSET,
|
|
ADPLL_MN2DIV_N2, width, 0);
|
|
if (err)
|
|
return err;
|
|
|
|
clock = devm_clk_register(d->dev, &d->dco.hw);
|
|
if (IS_ERR(clock))
|
|
return PTR_ERR(clock);
|
|
|
|
return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
|
|
init.name, NULL);
|
|
}
|
|
|
|
static int ti_adpll_clkout_enable(struct clk_hw *hw)
|
|
{
|
|
struct ti_adpll_clkout_data *co = to_clkout(hw);
|
|
struct clk_hw *gate_hw = &co->gate.hw;
|
|
|
|
__clk_hw_set_clk(gate_hw, hw);
|
|
|
|
return clk_gate_ops.enable(gate_hw);
|
|
}
|
|
|
|
static void ti_adpll_clkout_disable(struct clk_hw *hw)
|
|
{
|
|
struct ti_adpll_clkout_data *co = to_clkout(hw);
|
|
struct clk_hw *gate_hw = &co->gate.hw;
|
|
|
|
__clk_hw_set_clk(gate_hw, hw);
|
|
clk_gate_ops.disable(gate_hw);
|
|
}
|
|
|
|
static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct ti_adpll_clkout_data *co = to_clkout(hw);
|
|
struct clk_hw *gate_hw = &co->gate.hw;
|
|
|
|
__clk_hw_set_clk(gate_hw, hw);
|
|
|
|
return clk_gate_ops.is_enabled(gate_hw);
|
|
}
|
|
|
|
/* Setting PLL bypass puts clkout and clkoutx2 into bypass */
|
|
static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
|
|
{
|
|
struct ti_adpll_clkout_data *co = to_clkout(hw);
|
|
struct ti_adpll_data *d = co->adpll;
|
|
|
|
return ti_adpll_clock_is_bypass(d);
|
|
}
|
|
|
|
static int ti_adpll_init_clkout(struct ti_adpll_data *d,
|
|
enum ti_adpll_clocks index,
|
|
int output_index, int gate_bit,
|
|
char *name, struct clk *clk0,
|
|
struct clk *clk1)
|
|
{
|
|
struct ti_adpll_clkout_data *co;
|
|
struct clk_init_data init;
|
|
struct clk_ops *ops;
|
|
const char *parent_names[2];
|
|
const char *child_name;
|
|
struct clk *clock;
|
|
int err;
|
|
|
|
co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
|
|
if (!co)
|
|
return -ENOMEM;
|
|
co->adpll = d;
|
|
|
|
err = of_property_read_string_index(d->np,
|
|
"clock-output-names",
|
|
output_index,
|
|
&child_name);
|
|
if (err)
|
|
return err;
|
|
|
|
ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
|
|
if (!ops)
|
|
return -ENOMEM;
|
|
|
|
init.name = child_name;
|
|
init.ops = ops;
|
|
init.flags = CLK_IS_BASIC;
|
|
co->hw.init = &init;
|
|
parent_names[0] = __clk_get_name(clk0);
|
|
parent_names[1] = __clk_get_name(clk1);
|
|
init.parent_names = parent_names;
|
|
init.num_parents = 2;
|
|
|
|
ops->get_parent = ti_adpll_clkout_get_parent;
|
|
ops->determine_rate = __clk_mux_determine_rate;
|
|
if (gate_bit) {
|
|
co->gate.lock = &d->lock;
|
|
co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
|
|
co->gate.bit_idx = gate_bit;
|
|
ops->enable = ti_adpll_clkout_enable;
|
|
ops->disable = ti_adpll_clkout_disable;
|
|
ops->is_enabled = ti_adpll_clkout_is_enabled;
|
|
}
|
|
|
|
clock = devm_clk_register(d->dev, &co->hw);
|
|
if (IS_ERR(clock)) {
|
|
dev_err(d->dev, "failed to register output %s: %li\n",
|
|
name, PTR_ERR(clock));
|
|
return PTR_ERR(clock);
|
|
}
|
|
|
|
return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
|
|
NULL);
|
|
}
|
|
|
|
static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
|
|
{
|
|
int err;
|
|
|
|
if (!d->c->is_type_s)
|
|
return 0;
|
|
|
|
/* Internal mux, sources from divider N2 or clkinpulow */
|
|
err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
|
|
d->clocks[TI_ADPLL_N2].clk,
|
|
d->parent_clocks[TI_ADPLL_CLKINPULOW],
|
|
d->regs + ADPLL_CLKCTRL_OFFSET,
|
|
ADPLL_CLKCTRL_ULOWCLKEN);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Internal divider M2, sources DCO */
|
|
err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
|
|
d->clocks[TI_ADPLL_DCO].clk,
|
|
d->regs + ADPLL_M2NDIV_OFFSET,
|
|
ADPLL_M2NDIV_M2,
|
|
ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
|
|
CLK_DIVIDER_ONE_BASED);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Internal fixed divider, after M2 before clkout */
|
|
err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
|
|
d->clocks[TI_ADPLL_M2].clk,
|
|
1, 2);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Output clkout with a mux and gate, sources from div2 or bypass */
|
|
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
|
|
ADPLL_CLKCTRL_CLKOUTEN, "clkout",
|
|
d->clocks[TI_ADPLL_DIV2].clk,
|
|
d->clocks[TI_ADPLL_BYPASS].clk);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
|
|
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
|
|
"clkout2", d->clocks[TI_ADPLL_M2].clk,
|
|
d->clocks[TI_ADPLL_BYPASS].clk);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Internal mux, sources from DCO and clkinphif */
|
|
if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
|
|
err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
|
|
d->clocks[TI_ADPLL_DCO].clk,
|
|
d->parent_clocks[TI_ADPLL_CLKINPHIF],
|
|
d->regs + ADPLL_CLKCTRL_OFFSET,
|
|
ADPLL_CLKINPHIFSEL_ADPLL_S);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
/* Output clkouthif with a divider M3, sources from hif */
|
|
err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
|
|
d->clocks[TI_ADPLL_HIF].clk,
|
|
d->regs + ADPLL_M3DIV_OFFSET,
|
|
ADPLL_M3DIV_M3,
|
|
ADPLL_M3DIV_M3_WIDTH,
|
|
CLK_DIVIDER_ONE_BASED);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Output clock dcoclkldo is the DCO */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
|
|
{
|
|
int err;
|
|
|
|
if (d->c->is_type_s)
|
|
return 0;
|
|
|
|
/* Output clkdcoldo, gated output of DCO */
|
|
err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
|
|
"clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
|
|
d->regs + ADPLL_CLKCTRL_OFFSET,
|
|
ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Internal divider M2, sources from DCO */
|
|
err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
|
|
"m2", d->clocks[TI_ADPLL_DCO].clk,
|
|
d->regs + ADPLL_M2NDIV_OFFSET,
|
|
ADPLL_M2NDIV_M2,
|
|
ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
|
|
CLK_DIVIDER_ONE_BASED);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Output clkoutldo, gated output of M2 */
|
|
err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
|
|
"clkoutldo", d->clocks[TI_ADPLL_M2].clk,
|
|
d->regs + ADPLL_CLKCTRL_OFFSET,
|
|
ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
|
|
0);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Internal mux, sources from divider N2 or clkinpulow */
|
|
err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
|
|
d->clocks[TI_ADPLL_N2].clk,
|
|
d->parent_clocks[TI_ADPLL_CLKINPULOW],
|
|
d->regs + ADPLL_CLKCTRL_OFFSET,
|
|
ADPLL_CLKCTRL_ULOWCLKEN);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Output clkout, sources M2 or bypass */
|
|
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
|
|
ADPLL_CLKCTRL_CLKOUTEN, "clkout",
|
|
d->clocks[TI_ADPLL_M2].clk,
|
|
d->clocks[TI_ADPLL_BYPASS].clk);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ti_adpll_free_resources(struct ti_adpll_data *d)
|
|
{
|
|
int i;
|
|
|
|
for (i = TI_ADPLL_M3; i >= 0; i--) {
|
|
struct ti_adpll_clock *ac = &d->clocks[i];
|
|
|
|
if (!ac || IS_ERR_OR_NULL(ac->clk))
|
|
continue;
|
|
if (ac->cl)
|
|
clkdev_drop(ac->cl);
|
|
if (ac->unregister)
|
|
ac->unregister(ac->clk);
|
|
}
|
|
}
|
|
|
|
/* MPU PLL manages the lock register for all PLLs */
|
|
static void ti_adpll_unlock_all(void __iomem *reg)
|
|
{
|
|
u32 v;
|
|
|
|
v = readl_relaxed(reg);
|
|
if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
|
|
writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
|
|
}
|
|
|
|
static int ti_adpll_init_registers(struct ti_adpll_data *d)
|
|
{
|
|
int register_offset = 0;
|
|
|
|
if (d->c->is_type_s) {
|
|
register_offset = 8;
|
|
ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
|
|
}
|
|
|
|
d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ti_adpll_init_inputs(struct ti_adpll_data *d)
|
|
{
|
|
const char *error = "need at least %i inputs";
|
|
struct clk *clock;
|
|
int nr_inputs;
|
|
|
|
nr_inputs = of_clk_get_parent_count(d->np);
|
|
if (nr_inputs < d->c->nr_max_inputs) {
|
|
dev_err(d->dev, error, nr_inputs);
|
|
return -EINVAL;
|
|
}
|
|
of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
|
|
|
|
clock = devm_clk_get(d->dev, d->parent_names[0]);
|
|
if (IS_ERR(clock)) {
|
|
dev_err(d->dev, "could not get clkinp\n");
|
|
return PTR_ERR(clock);
|
|
}
|
|
d->parent_clocks[TI_ADPLL_CLKINP] = clock;
|
|
|
|
clock = devm_clk_get(d->dev, d->parent_names[1]);
|
|
if (IS_ERR(clock)) {
|
|
dev_err(d->dev, "could not get clkinpulow clock\n");
|
|
return PTR_ERR(clock);
|
|
}
|
|
d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
|
|
|
|
if (d->c->is_type_s) {
|
|
clock = devm_clk_get(d->dev, d->parent_names[2]);
|
|
if (IS_ERR(clock)) {
|
|
dev_err(d->dev, "could not get clkinphif clock\n");
|
|
return PTR_ERR(clock);
|
|
}
|
|
d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ti_adpll_platform_data ti_adpll_type_s = {
|
|
.is_type_s = true,
|
|
.nr_max_inputs = MAX_ADPLL_INPUTS,
|
|
.nr_max_outputs = MAX_ADPLL_OUTPUTS,
|
|
.output_index = TI_ADPLL_S_DCOCLKLDO,
|
|
};
|
|
|
|
static const struct ti_adpll_platform_data ti_adpll_type_lj = {
|
|
.is_type_s = false,
|
|
.nr_max_inputs = MAX_ADPLL_INPUTS - 1,
|
|
.nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
|
|
.output_index = -EINVAL,
|
|
};
|
|
|
|
static const struct of_device_id ti_adpll_match[] = {
|
|
{ .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
|
|
{ .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ti_adpll_match);
|
|
|
|
static int ti_adpll_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct device *dev = &pdev->dev;
|
|
const struct of_device_id *match;
|
|
const struct ti_adpll_platform_data *pdata;
|
|
struct ti_adpll_data *d;
|
|
struct resource *res;
|
|
int err;
|
|
|
|
match = of_match_device(ti_adpll_match, dev);
|
|
if (match)
|
|
pdata = match->data;
|
|
else
|
|
return -ENODEV;
|
|
|
|
d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
|
|
if (!d)
|
|
return -ENOMEM;
|
|
d->dev = dev;
|
|
d->np = node;
|
|
d->c = pdata;
|
|
dev_set_drvdata(d->dev, d);
|
|
spin_lock_init(&d->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
d->pa = res->start;
|
|
|
|
d->iobase = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(d->iobase)) {
|
|
dev_err(dev, "could not get IO base: %li\n",
|
|
PTR_ERR(d->iobase));
|
|
return PTR_ERR(d->iobase);
|
|
}
|
|
|
|
err = ti_adpll_init_registers(d);
|
|
if (err)
|
|
return err;
|
|
|
|
err = ti_adpll_init_inputs(d);
|
|
if (err)
|
|
return err;
|
|
|
|
d->clocks = devm_kzalloc(d->dev, sizeof(struct ti_adpll_clock) *
|
|
TI_ADPLL_NR_CLOCKS,
|
|
GFP_KERNEL);
|
|
if (!d->clocks)
|
|
return -ENOMEM;
|
|
|
|
err = ti_adpll_init_dco(d);
|
|
if (err) {
|
|
dev_err(dev, "could not register dco: %i\n", err);
|
|
goto free;
|
|
}
|
|
|
|
err = ti_adpll_init_children_adpll_s(d);
|
|
if (err)
|
|
goto free;
|
|
err = ti_adpll_init_children_adpll_lj(d);
|
|
if (err)
|
|
goto free;
|
|
|
|
err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
|
|
if (err)
|
|
goto free;
|
|
|
|
return 0;
|
|
|
|
free:
|
|
WARN_ON(1);
|
|
ti_adpll_free_resources(d);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int ti_adpll_remove(struct platform_device *pdev)
|
|
{
|
|
struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
|
|
|
|
ti_adpll_free_resources(d);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ti_adpll_driver = {
|
|
.driver = {
|
|
.name = "ti-adpll",
|
|
.of_match_table = ti_adpll_match,
|
|
},
|
|
.probe = ti_adpll_probe,
|
|
.remove = ti_adpll_remove,
|
|
};
|
|
|
|
static int __init ti_adpll_init(void)
|
|
{
|
|
return platform_driver_register(&ti_adpll_driver);
|
|
}
|
|
core_initcall(ti_adpll_init);
|
|
|
|
static void __exit ti_adpll_exit(void)
|
|
{
|
|
platform_driver_unregister(&ti_adpll_driver);
|
|
}
|
|
module_exit(ti_adpll_exit);
|
|
|
|
MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
|
|
MODULE_ALIAS("platform:dm814-adpll-clock");
|
|
MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
|
|
MODULE_LICENSE("GPL v2");
|