mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 17:46:45 +07:00
5459148b09
Add a function to configure a range of GPIOs function and pull in one go, mainly for the SDHCI and framebuffer helpers which tend to do this. Signed-off-by: Ben Dooks <ben-linux@fluff.org> [kgene.kim@samsung.com: Fix small comments] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
344 lines
6.6 KiB
C
344 lines
6.6 KiB
C
/* linux/arch/arm/plat-s3c/gpio-config.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008-2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C series GPIO configuration core
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
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{
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struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
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unsigned long flags;
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int offset;
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int ret;
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if (!chip)
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return -EINVAL;
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offset = pin - chip->chip.base;
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s3c_gpio_lock(chip, flags);
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ret = s3c_gpio_do_setcfg(chip, offset, config);
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s3c_gpio_unlock(chip, flags);
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return ret;
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}
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EXPORT_SYMBOL(s3c_gpio_cfgpin);
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int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
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unsigned int cfg)
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{
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int ret;
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for (; nr > 0; nr--, start++) {
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ret = s3c_gpio_cfgpin(start, cfg);
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if (ret != 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
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int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
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unsigned int cfg, s3c_gpio_pull_t pull)
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{
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int ret;
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for (; nr > 0; nr--, start++) {
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s3c_gpio_setpull(start, pull);
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ret = s3c_gpio_cfgpin(start, cfg);
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if (ret != 0)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
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unsigned s3c_gpio_getcfg(unsigned int pin)
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{
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struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
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unsigned long flags;
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unsigned ret = 0;
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int offset;
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if (chip) {
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offset = pin - chip->chip.base;
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s3c_gpio_lock(chip, flags);
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ret = s3c_gpio_do_getcfg(chip, offset);
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s3c_gpio_unlock(chip, flags);
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}
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return ret;
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}
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EXPORT_SYMBOL(s3c_gpio_getcfg);
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int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
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{
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struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
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unsigned long flags;
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int offset, ret;
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if (!chip)
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return -EINVAL;
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offset = pin - chip->chip.base;
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s3c_gpio_lock(chip, flags);
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ret = s3c_gpio_do_setpull(chip, offset, pull);
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s3c_gpio_unlock(chip, flags);
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return ret;
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}
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EXPORT_SYMBOL(s3c_gpio_setpull);
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#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
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int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
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unsigned int off, unsigned int cfg)
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{
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void __iomem *reg = chip->base;
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unsigned int shift = off;
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u32 con;
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if (s3c_gpio_is_cfg_special(cfg)) {
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cfg &= 0xf;
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/* Map output to 0, and SFN2 to 1 */
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cfg -= 1;
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if (cfg > 1)
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return -EINVAL;
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cfg <<= shift;
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}
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con = __raw_readl(reg);
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con &= ~(0x1 << shift);
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con |= cfg;
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__raw_writel(con, reg);
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return 0;
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}
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unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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u32 con;
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con = __raw_readl(chip->base);
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con >>= off;
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con &= 1;
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con++;
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return S3C_GPIO_SFN(con);
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}
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int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
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unsigned int off, unsigned int cfg)
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{
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void __iomem *reg = chip->base;
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unsigned int shift = off * 2;
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u32 con;
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if (s3c_gpio_is_cfg_special(cfg)) {
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cfg &= 0xf;
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if (cfg > 3)
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return -EINVAL;
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cfg <<= shift;
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}
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con = __raw_readl(reg);
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con &= ~(0x3 << shift);
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con |= cfg;
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__raw_writel(con, reg);
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return 0;
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}
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unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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u32 con;
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con = __raw_readl(chip->base);
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con >>= off * 2;
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con &= 3;
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/* this conversion works for IN and OUT as well as special mode */
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return S3C_GPIO_SPECIAL(con);
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}
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#endif
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#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
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int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
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unsigned int off, unsigned int cfg)
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{
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void __iomem *reg = chip->base;
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unsigned int shift = (off & 7) * 4;
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u32 con;
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if (off < 8 && chip->chip.ngpio > 8)
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reg -= 4;
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if (s3c_gpio_is_cfg_special(cfg)) {
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cfg &= 0xf;
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cfg <<= shift;
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}
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con = __raw_readl(reg);
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con &= ~(0xf << shift);
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con |= cfg;
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__raw_writel(con, reg);
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return 0;
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}
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unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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void __iomem *reg = chip->base;
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unsigned int shift = (off & 7) * 4;
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u32 con;
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if (off < 8 && chip->chip.ngpio > 8)
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reg -= 4;
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con = __raw_readl(reg);
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con >>= shift;
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con &= 0xf;
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/* this conversion works for IN and OUT as well as special mode */
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return S3C_GPIO_SPECIAL(con);
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}
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#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
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#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
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int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
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unsigned int off, s3c_gpio_pull_t pull)
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{
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void __iomem *reg = chip->base + 0x08;
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int shift = off * 2;
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u32 pup;
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pup = __raw_readl(reg);
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pup &= ~(3 << shift);
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pup |= pull << shift;
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__raw_writel(pup, reg);
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return 0;
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}
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s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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void __iomem *reg = chip->base + 0x08;
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int shift = off * 2;
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u32 pup = __raw_readl(reg);
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pup >>= shift;
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pup &= 0x3;
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return (__force s3c_gpio_pull_t)pup;
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}
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#endif
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#ifdef CONFIG_S3C_GPIO_PULL_UP
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int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
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unsigned int off, s3c_gpio_pull_t pull)
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{
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void __iomem *reg = chip->base + 0x08;
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u32 pup = __raw_readl(reg);
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pup = __raw_readl(reg);
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if (pup == S3C_GPIO_PULL_UP)
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pup &= ~(1 << off);
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else if (pup == S3C_GPIO_PULL_NONE)
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pup |= (1 << off);
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else
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return -EINVAL;
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__raw_writel(pup, reg);
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return 0;
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}
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s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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void __iomem *reg = chip->base + 0x08;
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u32 pup = __raw_readl(reg);
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pup &= (1 << off);
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return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
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}
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#endif /* CONFIG_S3C_GPIO_PULL_UP */
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#ifdef CONFIG_S5P_GPIO_DRVSTR
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s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
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{
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struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
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unsigned int off;
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void __iomem *reg;
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int shift;
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u32 drvstr;
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if (!chip)
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return -EINVAL;
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off = pin - chip->chip.base;
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shift = off * 2;
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reg = chip->base + 0x0C;
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drvstr = __raw_readl(reg);
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drvstr = drvstr >> shift;
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drvstr &= 0x3;
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return (__force s5p_gpio_drvstr_t)drvstr;
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}
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EXPORT_SYMBOL(s5p_gpio_get_drvstr);
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int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
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{
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struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
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unsigned int off;
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void __iomem *reg;
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int shift;
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u32 tmp;
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if (!chip)
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return -EINVAL;
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off = pin - chip->chip.base;
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shift = off * 2;
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reg = chip->base + 0x0C;
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tmp = __raw_readl(reg);
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tmp &= ~(0x3 << shift);
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tmp |= drvstr << shift;
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__raw_writel(tmp, reg);
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return 0;
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}
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EXPORT_SYMBOL(s5p_gpio_set_drvstr);
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#endif /* CONFIG_S5P_GPIO_DRVSTR */
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