AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-04 12:37:00 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
54293ec307
linux_dsm_epyc7002/arch/mips/include/asm/octeon
History
David Daney 54293ec307 MIPS: Add Cavium OCTEON processor CSR definitions 
Here we define the addresses and bit-fields of the Configuration and
Status Registers (CSRs) for some of the hardware functional units on
the OCTEON SOC.

Definitions are needed for:

CIU  -- Central Interrupt Unit.
GPIO -- General Purpose Input Output.
IOB  -- Input / Output {Busing,Bridge}.
IPD  -- Input Packet Data unit.
L2C  -- Level-2 Cache controller.
L2D  -- Level-2 Data cache.
L2T  -- Level-2 cache Tag.
LED  -- Light Emitting Diode controller.
MIO  -- Miscellaneous Input / Output.
POW  -- Packet Order / Work unit.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:20 +00:00
..
cvmx-ciu-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-gpio-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-iob-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-ipd-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-l2c-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-l2d-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-l2t-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-led-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-mio-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00
cvmx-pow-defs.h MIPS: Add Cavium OCTEON processor CSR definitions 2009-01-11 09:57:20 +00:00