mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 09:48:07 +07:00
5145d57ec5
Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
751 lines
20 KiB
C
751 lines
20 KiB
C
/*
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* Copyright 2012-2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef V9_STRUCTS_H_
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#define V9_STRUCTS_H_
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struct v9_sdma_mqd {
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uint32_t sdmax_rlcx_rb_cntl;
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uint32_t sdmax_rlcx_rb_base;
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uint32_t sdmax_rlcx_rb_base_hi;
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uint32_t sdmax_rlcx_rb_rptr;
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uint32_t sdmax_rlcx_rb_rptr_hi;
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uint32_t sdmax_rlcx_rb_wptr;
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uint32_t sdmax_rlcx_rb_wptr_hi;
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uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
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uint32_t sdmax_rlcx_rb_rptr_addr_hi;
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uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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uint32_t sdmax_rlcx_ib_cntl;
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uint32_t sdmax_rlcx_ib_rptr;
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uint32_t sdmax_rlcx_ib_offset;
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uint32_t sdmax_rlcx_ib_base_lo;
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uint32_t sdmax_rlcx_ib_base_hi;
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uint32_t sdmax_rlcx_ib_size;
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uint32_t sdmax_rlcx_skip_cntl;
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uint32_t sdmax_rlcx_context_status;
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uint32_t sdmax_rlcx_doorbell;
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uint32_t sdmax_rlcx_status;
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uint32_t sdmax_rlcx_doorbell_log;
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uint32_t sdmax_rlcx_watermark;
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uint32_t sdmax_rlcx_doorbell_offset;
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uint32_t sdmax_rlcx_csa_addr_lo;
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uint32_t sdmax_rlcx_csa_addr_hi;
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uint32_t sdmax_rlcx_ib_sub_remain;
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uint32_t sdmax_rlcx_preempt;
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uint32_t sdmax_rlcx_dummy_reg;
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uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
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uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
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uint32_t sdmax_rlcx_rb_aql_cntl;
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uint32_t sdmax_rlcx_minor_ptr_update;
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uint32_t sdmax_rlcx_midcmd_data0;
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uint32_t sdmax_rlcx_midcmd_data1;
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uint32_t sdmax_rlcx_midcmd_data2;
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uint32_t sdmax_rlcx_midcmd_data3;
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uint32_t sdmax_rlcx_midcmd_data4;
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uint32_t sdmax_rlcx_midcmd_data5;
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uint32_t sdmax_rlcx_midcmd_data6;
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uint32_t sdmax_rlcx_midcmd_data7;
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uint32_t sdmax_rlcx_midcmd_data8;
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uint32_t sdmax_rlcx_midcmd_cntl;
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uint32_t reserved_42;
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uint32_t reserved_43;
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uint32_t reserved_44;
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uint32_t reserved_45;
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uint32_t reserved_46;
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uint32_t reserved_47;
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uint32_t reserved_48;
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uint32_t reserved_49;
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uint32_t reserved_50;
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uint32_t reserved_51;
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uint32_t reserved_52;
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uint32_t reserved_53;
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uint32_t reserved_54;
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uint32_t reserved_55;
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uint32_t reserved_56;
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uint32_t reserved_57;
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uint32_t reserved_58;
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uint32_t reserved_59;
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uint32_t reserved_60;
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uint32_t reserved_61;
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uint32_t reserved_62;
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uint32_t reserved_63;
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uint32_t reserved_64;
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uint32_t reserved_65;
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uint32_t reserved_66;
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uint32_t reserved_67;
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uint32_t reserved_68;
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uint32_t reserved_69;
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uint32_t reserved_70;
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uint32_t reserved_71;
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uint32_t reserved_72;
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uint32_t reserved_73;
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uint32_t reserved_74;
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uint32_t reserved_75;
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uint32_t reserved_76;
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uint32_t reserved_77;
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uint32_t reserved_78;
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uint32_t reserved_79;
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uint32_t reserved_80;
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uint32_t reserved_81;
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uint32_t reserved_82;
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uint32_t reserved_83;
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uint32_t reserved_84;
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uint32_t reserved_85;
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uint32_t reserved_86;
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uint32_t reserved_87;
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uint32_t reserved_88;
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uint32_t reserved_89;
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uint32_t reserved_90;
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uint32_t reserved_91;
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uint32_t reserved_92;
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uint32_t reserved_93;
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uint32_t reserved_94;
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uint32_t reserved_95;
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uint32_t reserved_96;
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uint32_t reserved_97;
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uint32_t reserved_98;
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uint32_t reserved_99;
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uint32_t reserved_100;
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uint32_t reserved_101;
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uint32_t reserved_102;
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uint32_t reserved_103;
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uint32_t reserved_104;
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uint32_t reserved_105;
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uint32_t reserved_106;
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uint32_t reserved_107;
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uint32_t reserved_108;
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uint32_t reserved_109;
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uint32_t reserved_110;
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uint32_t reserved_111;
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uint32_t reserved_112;
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uint32_t reserved_113;
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uint32_t reserved_114;
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uint32_t reserved_115;
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uint32_t reserved_116;
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uint32_t reserved_117;
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uint32_t reserved_118;
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uint32_t reserved_119;
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uint32_t reserved_120;
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uint32_t reserved_121;
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uint32_t reserved_122;
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uint32_t reserved_123;
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uint32_t reserved_124;
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uint32_t reserved_125;
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/* reserved_126,127: repurposed for driver-internal use */
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uint32_t sdma_engine_id;
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uint32_t sdma_queue_id;
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};
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struct v9_mqd {
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uint32_t header;
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uint32_t compute_dispatch_initiator;
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uint32_t compute_dim_x;
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uint32_t compute_dim_y;
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uint32_t compute_dim_z;
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uint32_t compute_start_x;
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uint32_t compute_start_y;
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uint32_t compute_start_z;
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uint32_t compute_num_thread_x;
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uint32_t compute_num_thread_y;
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uint32_t compute_num_thread_z;
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uint32_t compute_pipelinestat_enable;
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uint32_t compute_perfcount_enable;
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uint32_t compute_pgm_lo;
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uint32_t compute_pgm_hi;
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uint32_t compute_tba_lo;
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uint32_t compute_tba_hi;
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uint32_t compute_tma_lo;
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uint32_t compute_tma_hi;
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uint32_t compute_pgm_rsrc1;
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uint32_t compute_pgm_rsrc2;
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uint32_t compute_vmid;
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uint32_t compute_resource_limits;
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uint32_t compute_static_thread_mgmt_se0;
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uint32_t compute_static_thread_mgmt_se1;
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uint32_t compute_tmpring_size;
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uint32_t compute_static_thread_mgmt_se2;
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uint32_t compute_static_thread_mgmt_se3;
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uint32_t compute_restart_x;
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uint32_t compute_restart_y;
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uint32_t compute_restart_z;
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uint32_t compute_thread_trace_enable;
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uint32_t compute_misc_reserved;
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uint32_t compute_dispatch_id;
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uint32_t compute_threadgroup_id;
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uint32_t compute_relaunch;
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uint32_t compute_wave_restore_addr_lo;
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uint32_t compute_wave_restore_addr_hi;
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uint32_t compute_wave_restore_control;
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uint32_t compute_static_thread_mgmt_se4;
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uint32_t compute_static_thread_mgmt_se5;
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uint32_t compute_static_thread_mgmt_se6;
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uint32_t compute_static_thread_mgmt_se7;
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uint32_t reserved_43;
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uint32_t reserved_44;
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uint32_t reserved_45;
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uint32_t reserved_46;
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uint32_t reserved_47;
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uint32_t reserved_48;
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uint32_t reserved_49;
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uint32_t reserved_50;
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uint32_t reserved_51;
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uint32_t reserved_52;
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uint32_t reserved_53;
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uint32_t reserved_54;
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uint32_t reserved_55;
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uint32_t reserved_56;
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uint32_t reserved_57;
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uint32_t reserved_58;
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uint32_t reserved_59;
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uint32_t reserved_60;
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uint32_t reserved_61;
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uint32_t reserved_62;
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uint32_t reserved_63;
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uint32_t reserved_64;
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uint32_t compute_user_data_0;
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uint32_t compute_user_data_1;
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uint32_t compute_user_data_2;
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uint32_t compute_user_data_3;
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uint32_t compute_user_data_4;
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uint32_t compute_user_data_5;
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uint32_t compute_user_data_6;
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uint32_t compute_user_data_7;
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uint32_t compute_user_data_8;
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uint32_t compute_user_data_9;
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uint32_t compute_user_data_10;
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uint32_t compute_user_data_11;
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uint32_t compute_user_data_12;
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uint32_t compute_user_data_13;
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uint32_t compute_user_data_14;
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uint32_t compute_user_data_15;
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uint32_t cp_compute_csinvoc_count_lo;
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uint32_t cp_compute_csinvoc_count_hi;
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uint32_t reserved_83;
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uint32_t reserved_84;
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uint32_t reserved_85;
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uint32_t cp_mqd_query_time_lo;
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uint32_t cp_mqd_query_time_hi;
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uint32_t cp_mqd_connect_start_time_lo;
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uint32_t cp_mqd_connect_start_time_hi;
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uint32_t cp_mqd_connect_end_time_lo;
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uint32_t cp_mqd_connect_end_time_hi;
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uint32_t cp_mqd_connect_end_wf_count;
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uint32_t cp_mqd_connect_end_pq_rptr;
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uint32_t cp_mqd_connect_end_pq_wptr;
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uint32_t cp_mqd_connect_end_ib_rptr;
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uint32_t cp_mqd_readindex_lo;
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uint32_t cp_mqd_readindex_hi;
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uint32_t cp_mqd_save_start_time_lo;
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uint32_t cp_mqd_save_start_time_hi;
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uint32_t cp_mqd_save_end_time_lo;
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uint32_t cp_mqd_save_end_time_hi;
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uint32_t cp_mqd_restore_start_time_lo;
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uint32_t cp_mqd_restore_start_time_hi;
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uint32_t cp_mqd_restore_end_time_lo;
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uint32_t cp_mqd_restore_end_time_hi;
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uint32_t disable_queue;
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uint32_t reserved_107;
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uint32_t gds_cs_ctxsw_cnt0;
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uint32_t gds_cs_ctxsw_cnt1;
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uint32_t gds_cs_ctxsw_cnt2;
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uint32_t gds_cs_ctxsw_cnt3;
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uint32_t reserved_112;
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uint32_t reserved_113;
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uint32_t cp_pq_exe_status_lo;
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uint32_t cp_pq_exe_status_hi;
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uint32_t cp_packet_id_lo;
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uint32_t cp_packet_id_hi;
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uint32_t cp_packet_exe_status_lo;
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uint32_t cp_packet_exe_status_hi;
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uint32_t gds_save_base_addr_lo;
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uint32_t gds_save_base_addr_hi;
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uint32_t gds_save_mask_lo;
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uint32_t gds_save_mask_hi;
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uint32_t ctx_save_base_addr_lo;
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uint32_t ctx_save_base_addr_hi;
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uint32_t dynamic_cu_mask_addr_lo;
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uint32_t dynamic_cu_mask_addr_hi;
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uint32_t cp_mqd_base_addr_lo;
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uint32_t cp_mqd_base_addr_hi;
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uint32_t cp_hqd_active;
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uint32_t cp_hqd_vmid;
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uint32_t cp_hqd_persistent_state;
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uint32_t cp_hqd_pipe_priority;
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uint32_t cp_hqd_queue_priority;
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uint32_t cp_hqd_quantum;
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uint32_t cp_hqd_pq_base_lo;
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uint32_t cp_hqd_pq_base_hi;
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uint32_t cp_hqd_pq_rptr;
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uint32_t cp_hqd_pq_rptr_report_addr_lo;
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uint32_t cp_hqd_pq_rptr_report_addr_hi;
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uint32_t cp_hqd_pq_wptr_poll_addr_lo;
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uint32_t cp_hqd_pq_wptr_poll_addr_hi;
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uint32_t cp_hqd_pq_doorbell_control;
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uint32_t reserved_144;
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uint32_t cp_hqd_pq_control;
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uint32_t cp_hqd_ib_base_addr_lo;
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uint32_t cp_hqd_ib_base_addr_hi;
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uint32_t cp_hqd_ib_rptr;
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uint32_t cp_hqd_ib_control;
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uint32_t cp_hqd_iq_timer;
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uint32_t cp_hqd_iq_rptr;
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uint32_t cp_hqd_dequeue_request;
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uint32_t cp_hqd_dma_offload;
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uint32_t cp_hqd_sema_cmd;
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uint32_t cp_hqd_msg_type;
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uint32_t cp_hqd_atomic0_preop_lo;
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uint32_t cp_hqd_atomic0_preop_hi;
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uint32_t cp_hqd_atomic1_preop_lo;
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uint32_t cp_hqd_atomic1_preop_hi;
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uint32_t cp_hqd_hq_status0;
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uint32_t cp_hqd_hq_control0;
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uint32_t cp_mqd_control;
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uint32_t cp_hqd_hq_status1;
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uint32_t cp_hqd_hq_control1;
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uint32_t cp_hqd_eop_base_addr_lo;
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uint32_t cp_hqd_eop_base_addr_hi;
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uint32_t cp_hqd_eop_control;
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uint32_t cp_hqd_eop_rptr;
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uint32_t cp_hqd_eop_wptr;
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uint32_t cp_hqd_eop_done_events;
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uint32_t cp_hqd_ctx_save_base_addr_lo;
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uint32_t cp_hqd_ctx_save_base_addr_hi;
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uint32_t cp_hqd_ctx_save_control;
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uint32_t cp_hqd_cntl_stack_offset;
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uint32_t cp_hqd_cntl_stack_size;
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uint32_t cp_hqd_wg_state_offset;
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uint32_t cp_hqd_ctx_save_size;
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uint32_t cp_hqd_gds_resource_state;
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uint32_t cp_hqd_error;
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uint32_t cp_hqd_eop_wptr_mem;
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uint32_t cp_hqd_aql_control;
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uint32_t cp_hqd_pq_wptr_lo;
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uint32_t cp_hqd_pq_wptr_hi;
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uint32_t reserved_184;
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uint32_t reserved_185;
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uint32_t reserved_186;
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uint32_t reserved_187;
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uint32_t reserved_188;
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uint32_t reserved_189;
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uint32_t reserved_190;
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uint32_t reserved_191;
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uint32_t iqtimer_pkt_header;
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uint32_t iqtimer_pkt_dw0;
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uint32_t iqtimer_pkt_dw1;
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uint32_t iqtimer_pkt_dw2;
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uint32_t iqtimer_pkt_dw3;
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uint32_t iqtimer_pkt_dw4;
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uint32_t iqtimer_pkt_dw5;
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uint32_t iqtimer_pkt_dw6;
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uint32_t iqtimer_pkt_dw7;
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uint32_t iqtimer_pkt_dw8;
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uint32_t iqtimer_pkt_dw9;
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uint32_t iqtimer_pkt_dw10;
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uint32_t iqtimer_pkt_dw11;
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uint32_t iqtimer_pkt_dw12;
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uint32_t iqtimer_pkt_dw13;
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uint32_t iqtimer_pkt_dw14;
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uint32_t iqtimer_pkt_dw15;
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uint32_t iqtimer_pkt_dw16;
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uint32_t iqtimer_pkt_dw17;
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uint32_t iqtimer_pkt_dw18;
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uint32_t iqtimer_pkt_dw19;
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uint32_t iqtimer_pkt_dw20;
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uint32_t iqtimer_pkt_dw21;
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uint32_t iqtimer_pkt_dw22;
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uint32_t iqtimer_pkt_dw23;
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uint32_t iqtimer_pkt_dw24;
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uint32_t iqtimer_pkt_dw25;
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uint32_t iqtimer_pkt_dw26;
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uint32_t iqtimer_pkt_dw27;
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uint32_t iqtimer_pkt_dw28;
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uint32_t iqtimer_pkt_dw29;
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uint32_t iqtimer_pkt_dw30;
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uint32_t iqtimer_pkt_dw31;
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uint32_t reserved_225;
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uint32_t reserved_226;
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uint32_t reserved_227;
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uint32_t set_resources_header;
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uint32_t set_resources_dw1;
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uint32_t set_resources_dw2;
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uint32_t set_resources_dw3;
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uint32_t set_resources_dw4;
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uint32_t set_resources_dw5;
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uint32_t set_resources_dw6;
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uint32_t set_resources_dw7;
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uint32_t reserved_236;
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uint32_t reserved_237;
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uint32_t reserved_238;
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uint32_t reserved_239;
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uint32_t queue_doorbell_id0;
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uint32_t queue_doorbell_id1;
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uint32_t queue_doorbell_id2;
|
|
uint32_t queue_doorbell_id3;
|
|
uint32_t queue_doorbell_id4;
|
|
uint32_t queue_doorbell_id5;
|
|
uint32_t queue_doorbell_id6;
|
|
uint32_t queue_doorbell_id7;
|
|
uint32_t queue_doorbell_id8;
|
|
uint32_t queue_doorbell_id9;
|
|
uint32_t queue_doorbell_id10;
|
|
uint32_t queue_doorbell_id11;
|
|
uint32_t queue_doorbell_id12;
|
|
uint32_t queue_doorbell_id13;
|
|
uint32_t queue_doorbell_id14;
|
|
uint32_t queue_doorbell_id15;
|
|
uint32_t reserved_256;
|
|
uint32_t reserved_257;
|
|
uint32_t reserved_258;
|
|
uint32_t reserved_259;
|
|
uint32_t reserved_260;
|
|
uint32_t reserved_261;
|
|
uint32_t reserved_262;
|
|
uint32_t reserved_263;
|
|
uint32_t reserved_264;
|
|
uint32_t reserved_265;
|
|
uint32_t reserved_266;
|
|
uint32_t reserved_267;
|
|
uint32_t reserved_268;
|
|
uint32_t reserved_269;
|
|
uint32_t reserved_270;
|
|
uint32_t reserved_271;
|
|
uint32_t reserved_272;
|
|
uint32_t reserved_273;
|
|
uint32_t reserved_274;
|
|
uint32_t reserved_275;
|
|
uint32_t reserved_276;
|
|
uint32_t reserved_277;
|
|
uint32_t reserved_278;
|
|
uint32_t reserved_279;
|
|
uint32_t reserved_280;
|
|
uint32_t reserved_281;
|
|
uint32_t reserved_282;
|
|
uint32_t reserved_283;
|
|
uint32_t reserved_284;
|
|
uint32_t reserved_285;
|
|
uint32_t reserved_286;
|
|
uint32_t reserved_287;
|
|
uint32_t reserved_288;
|
|
uint32_t reserved_289;
|
|
uint32_t reserved_290;
|
|
uint32_t reserved_291;
|
|
uint32_t reserved_292;
|
|
uint32_t reserved_293;
|
|
uint32_t reserved_294;
|
|
uint32_t reserved_295;
|
|
uint32_t reserved_296;
|
|
uint32_t reserved_297;
|
|
uint32_t reserved_298;
|
|
uint32_t reserved_299;
|
|
uint32_t reserved_300;
|
|
uint32_t reserved_301;
|
|
uint32_t reserved_302;
|
|
uint32_t reserved_303;
|
|
uint32_t reserved_304;
|
|
uint32_t reserved_305;
|
|
uint32_t reserved_306;
|
|
uint32_t reserved_307;
|
|
uint32_t reserved_308;
|
|
uint32_t reserved_309;
|
|
uint32_t reserved_310;
|
|
uint32_t reserved_311;
|
|
uint32_t reserved_312;
|
|
uint32_t reserved_313;
|
|
uint32_t reserved_314;
|
|
uint32_t reserved_315;
|
|
uint32_t reserved_316;
|
|
uint32_t reserved_317;
|
|
uint32_t reserved_318;
|
|
uint32_t reserved_319;
|
|
uint32_t reserved_320;
|
|
uint32_t reserved_321;
|
|
uint32_t reserved_322;
|
|
uint32_t reserved_323;
|
|
uint32_t reserved_324;
|
|
uint32_t reserved_325;
|
|
uint32_t reserved_326;
|
|
uint32_t reserved_327;
|
|
uint32_t reserved_328;
|
|
uint32_t reserved_329;
|
|
uint32_t reserved_330;
|
|
uint32_t reserved_331;
|
|
uint32_t reserved_332;
|
|
uint32_t reserved_333;
|
|
uint32_t reserved_334;
|
|
uint32_t reserved_335;
|
|
uint32_t reserved_336;
|
|
uint32_t reserved_337;
|
|
uint32_t reserved_338;
|
|
uint32_t reserved_339;
|
|
uint32_t reserved_340;
|
|
uint32_t reserved_341;
|
|
uint32_t reserved_342;
|
|
uint32_t reserved_343;
|
|
uint32_t reserved_344;
|
|
uint32_t reserved_345;
|
|
uint32_t reserved_346;
|
|
uint32_t reserved_347;
|
|
uint32_t reserved_348;
|
|
uint32_t reserved_349;
|
|
uint32_t reserved_350;
|
|
uint32_t reserved_351;
|
|
uint32_t reserved_352;
|
|
uint32_t reserved_353;
|
|
uint32_t reserved_354;
|
|
uint32_t reserved_355;
|
|
uint32_t reserved_356;
|
|
uint32_t reserved_357;
|
|
uint32_t reserved_358;
|
|
uint32_t reserved_359;
|
|
uint32_t reserved_360;
|
|
uint32_t reserved_361;
|
|
uint32_t reserved_362;
|
|
uint32_t reserved_363;
|
|
uint32_t reserved_364;
|
|
uint32_t reserved_365;
|
|
uint32_t reserved_366;
|
|
uint32_t reserved_367;
|
|
uint32_t reserved_368;
|
|
uint32_t reserved_369;
|
|
uint32_t reserved_370;
|
|
uint32_t reserved_371;
|
|
uint32_t reserved_372;
|
|
uint32_t reserved_373;
|
|
uint32_t reserved_374;
|
|
uint32_t reserved_375;
|
|
uint32_t reserved_376;
|
|
uint32_t reserved_377;
|
|
uint32_t reserved_378;
|
|
uint32_t reserved_379;
|
|
uint32_t reserved_380;
|
|
uint32_t reserved_381;
|
|
uint32_t reserved_382;
|
|
uint32_t reserved_383;
|
|
uint32_t reserved_384;
|
|
uint32_t reserved_385;
|
|
uint32_t reserved_386;
|
|
uint32_t reserved_387;
|
|
uint32_t reserved_388;
|
|
uint32_t reserved_389;
|
|
uint32_t reserved_390;
|
|
uint32_t reserved_391;
|
|
uint32_t reserved_392;
|
|
uint32_t reserved_393;
|
|
uint32_t reserved_394;
|
|
uint32_t reserved_395;
|
|
uint32_t reserved_396;
|
|
uint32_t reserved_397;
|
|
uint32_t reserved_398;
|
|
uint32_t reserved_399;
|
|
uint32_t reserved_400;
|
|
uint32_t reserved_401;
|
|
uint32_t reserved_402;
|
|
uint32_t reserved_403;
|
|
uint32_t reserved_404;
|
|
uint32_t reserved_405;
|
|
uint32_t reserved_406;
|
|
uint32_t reserved_407;
|
|
uint32_t reserved_408;
|
|
uint32_t reserved_409;
|
|
uint32_t reserved_410;
|
|
uint32_t reserved_411;
|
|
uint32_t reserved_412;
|
|
uint32_t reserved_413;
|
|
uint32_t reserved_414;
|
|
uint32_t reserved_415;
|
|
uint32_t reserved_416;
|
|
uint32_t reserved_417;
|
|
uint32_t reserved_418;
|
|
uint32_t reserved_419;
|
|
uint32_t reserved_420;
|
|
uint32_t reserved_421;
|
|
uint32_t reserved_422;
|
|
uint32_t reserved_423;
|
|
uint32_t reserved_424;
|
|
uint32_t reserved_425;
|
|
uint32_t reserved_426;
|
|
uint32_t reserved_427;
|
|
uint32_t reserved_428;
|
|
uint32_t reserved_429;
|
|
uint32_t reserved_430;
|
|
uint32_t reserved_431;
|
|
uint32_t reserved_432;
|
|
uint32_t reserved_433;
|
|
uint32_t reserved_434;
|
|
uint32_t reserved_435;
|
|
uint32_t reserved_436;
|
|
uint32_t reserved_437;
|
|
uint32_t reserved_438;
|
|
uint32_t reserved_439;
|
|
uint32_t reserved_440;
|
|
uint32_t reserved_441;
|
|
uint32_t reserved_442;
|
|
uint32_t reserved_443;
|
|
uint32_t reserved_444;
|
|
uint32_t reserved_445;
|
|
uint32_t reserved_446;
|
|
uint32_t reserved_447;
|
|
uint32_t reserved_448;
|
|
uint32_t reserved_449;
|
|
uint32_t reserved_450;
|
|
uint32_t reserved_451;
|
|
uint32_t reserved_452;
|
|
uint32_t reserved_453;
|
|
uint32_t reserved_454;
|
|
uint32_t reserved_455;
|
|
uint32_t reserved_456;
|
|
uint32_t reserved_457;
|
|
uint32_t reserved_458;
|
|
uint32_t reserved_459;
|
|
uint32_t reserved_460;
|
|
uint32_t reserved_461;
|
|
uint32_t reserved_462;
|
|
uint32_t reserved_463;
|
|
uint32_t reserved_464;
|
|
uint32_t reserved_465;
|
|
uint32_t reserved_466;
|
|
uint32_t reserved_467;
|
|
uint32_t reserved_468;
|
|
uint32_t reserved_469;
|
|
uint32_t reserved_470;
|
|
uint32_t reserved_471;
|
|
uint32_t reserved_472;
|
|
uint32_t reserved_473;
|
|
uint32_t reserved_474;
|
|
uint32_t reserved_475;
|
|
uint32_t reserved_476;
|
|
uint32_t reserved_477;
|
|
uint32_t reserved_478;
|
|
uint32_t reserved_479;
|
|
uint32_t reserved_480;
|
|
uint32_t reserved_481;
|
|
uint32_t reserved_482;
|
|
uint32_t reserved_483;
|
|
uint32_t reserved_484;
|
|
uint32_t reserved_485;
|
|
uint32_t reserved_486;
|
|
uint32_t reserved_487;
|
|
uint32_t reserved_488;
|
|
uint32_t reserved_489;
|
|
uint32_t reserved_490;
|
|
uint32_t reserved_491;
|
|
uint32_t reserved_492;
|
|
uint32_t reserved_493;
|
|
uint32_t reserved_494;
|
|
uint32_t reserved_495;
|
|
uint32_t reserved_496;
|
|
uint32_t reserved_497;
|
|
uint32_t reserved_498;
|
|
uint32_t reserved_499;
|
|
uint32_t reserved_500;
|
|
uint32_t reserved_501;
|
|
uint32_t reserved_502;
|
|
uint32_t reserved_503;
|
|
uint32_t reserved_504;
|
|
uint32_t reserved_505;
|
|
uint32_t reserved_506;
|
|
uint32_t reserved_507;
|
|
uint32_t reserved_508;
|
|
uint32_t reserved_509;
|
|
uint32_t reserved_510;
|
|
uint32_t reserved_511;
|
|
};
|
|
|
|
struct v9_mqd_allocation {
|
|
struct v9_mqd mqd;
|
|
uint32_t wptr_poll_mem;
|
|
uint32_t rptr_report_mem;
|
|
uint32_t dynamic_cu_mask;
|
|
uint32_t dynamic_rb_mask;
|
|
};
|
|
|
|
/* from vega10 all CSA format is shifted to chain ib compatible mode */
|
|
struct v9_ce_ib_state {
|
|
/* section of non chained ib part */
|
|
uint32_t ce_ib_completion_status;
|
|
uint32_t ce_constegnine_count;
|
|
uint32_t ce_ibOffset_ib1;
|
|
uint32_t ce_ibOffset_ib2;
|
|
|
|
/* section of chained ib */
|
|
uint32_t ce_chainib_addrlo_ib1;
|
|
uint32_t ce_chainib_addrlo_ib2;
|
|
uint32_t ce_chainib_addrhi_ib1;
|
|
uint32_t ce_chainib_addrhi_ib2;
|
|
uint32_t ce_chainib_size_ib1;
|
|
uint32_t ce_chainib_size_ib2;
|
|
}; /* total 10 DWORD */
|
|
|
|
struct v9_de_ib_state {
|
|
/* section of non chained ib part */
|
|
uint32_t ib_completion_status;
|
|
uint32_t de_constEngine_count;
|
|
uint32_t ib_offset_ib1;
|
|
uint32_t ib_offset_ib2;
|
|
|
|
/* section of chained ib */
|
|
uint32_t chain_ib_addrlo_ib1;
|
|
uint32_t chain_ib_addrlo_ib2;
|
|
uint32_t chain_ib_addrhi_ib1;
|
|
uint32_t chain_ib_addrhi_ib2;
|
|
uint32_t chain_ib_size_ib1;
|
|
uint32_t chain_ib_size_ib2;
|
|
|
|
/* section of non chained ib part */
|
|
uint32_t preamble_begin_ib1;
|
|
uint32_t preamble_begin_ib2;
|
|
uint32_t preamble_end_ib1;
|
|
uint32_t preamble_end_ib2;
|
|
|
|
/* section of chained ib */
|
|
uint32_t chain_ib_pream_addrlo_ib1;
|
|
uint32_t chain_ib_pream_addrlo_ib2;
|
|
uint32_t chain_ib_pream_addrhi_ib1;
|
|
uint32_t chain_ib_pream_addrhi_ib2;
|
|
|
|
/* section of non chained ib part */
|
|
uint32_t draw_indirect_baseLo;
|
|
uint32_t draw_indirect_baseHi;
|
|
uint32_t disp_indirect_baseLo;
|
|
uint32_t disp_indirect_baseHi;
|
|
uint32_t gds_backup_addrlo;
|
|
uint32_t gds_backup_addrhi;
|
|
uint32_t index_base_addrlo;
|
|
uint32_t index_base_addrhi;
|
|
uint32_t sample_cntl;
|
|
}; /* Total of 27 DWORD */
|
|
|
|
struct v9_gfx_meta_data {
|
|
/* 10 DWORD, address must be 4KB aligned */
|
|
struct v9_ce_ib_state ce_payload;
|
|
uint32_t reserved1[54];
|
|
/* 27 DWORD, address must be 64B aligned */
|
|
struct v9_de_ib_state de_payload;
|
|
/* PFP IB base address which get pre-empted */
|
|
uint32_t DeIbBaseAddrLo;
|
|
uint32_t DeIbBaseAddrHi;
|
|
uint32_t reserved2[931];
|
|
}; /* Total of 4K Bytes */
|
|
|
|
#endif /* V9_STRUCTS_H_ */
|