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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e8c165fec9
This patch adds the pinctrl configuration for the mt6797 EVB. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
271 lines
6.3 KiB
Plaintext
271 lines
6.3 KiB
Plaintext
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt6797-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
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/ {
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compatible = "mediatek,mt6797";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x001>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x002>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x003>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x102>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x103>;
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};
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cpu8: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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reg = <0x200>;
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};
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cpu9: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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enable-method = "psci";
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reg = <0x201>;
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};
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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topckgen: topckgen@10000000 {
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compatible = "mediatek,mt6797-topckgen";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infrasys: infracfg_ao@10001000 {
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compatible = "mediatek,mt6797-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6797-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x10002000 0 0x400>,
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<0 0x10002400 0 0x400>,
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<0 0x10002800 0 0x400>,
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<0 0x10002C00 0 0x400>;
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reg-names = "gpio", "iocfgl", "iocfgb",
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"iocfgr", "iocfgt";
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gpio-controller;
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#gpio-cells = <2>;
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uart0_pins_a: uart0 {
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pins0 {
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pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
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<MT6797_GPIO235__FUNC_URXD0>;
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};
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};
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uart1_pins_a: uart1 {
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pins1 {
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pinmux = <MT6797_GPIO232__FUNC_URXD1>,
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<MT6797_GPIO233__FUNC_UTXD1>;
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};
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};
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt6797-scpsys";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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clocks = <&topckgen CLK_TOP_MUX_MFG>,
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<&topckgen CLK_TOP_MUX_MM>,
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<&topckgen CLK_TOP_MUX_VDEC>;
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clock-names = "mfg", "mm", "vdec";
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infracfg = <&infrasys>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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apmixedsys: apmixed@1000c000 {
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compatible = "mediatek,mt6797-apmixedsys";
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reg = <0 0x1000c000 0 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: intpol-controller@10200620 {
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compatible = "mediatek,mt6797-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10220620 0 0x20>,
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<0 0x10220690 0 0x10>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt6797-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_UART0>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt6797-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_UART1>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt6797-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_UART2>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt6797-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_UART3>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmsys: mmsys_config@14000000 {
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compatible = "mediatek,mt6797-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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imgsys: imgsys_config@15000000 {
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compatible = "mediatek,mt6797-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: vdec_gcon@16000000 {
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compatible = "mediatek,mt6797-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x10000>;
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#clock-cells = <1>;
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};
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vencsys: venc_gcon@17000000 {
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compatible = "mediatek,mt6797-vencsys", "syscon";
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reg = <0 0x17000000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@19000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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reg = <0 0x19000000 0 0x10000>, /* GICD */
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<0 0x19200000 0 0x200000>, /* GICR */
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<0 0x10240000 0 0x2000>; /* GICC */
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};
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};
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