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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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52393ccc0a
set_wmb should not be used in the kernel because it just confuses the
code more and has no benefit. Since it is not currently used in the
kernel this patch removes it so that new code does not include it.
All archs define set_wmb(var, value) to do { var = value; wmb(); }
while(0) except ia64 and sparc which use a mb() instead. But this is
still moot since it is not used anyway.
Hasn't been tested on any archs but x86 and x86_64 (and only compiled
tested)
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
201 lines
5.1 KiB
C
201 lines
5.1 KiB
C
/* system.h: FR-V CPU control definitions
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/linkage.h>
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#include <asm/atomic.h>
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struct thread_struct;
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'.
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* The `mb' is to tell GCC not to cache `current' across this call.
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*/
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extern asmlinkage
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struct task_struct *__switch_to(struct thread_struct *prev_thread,
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struct thread_struct *next_thread,
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struct task_struct *prev);
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#define switch_to(prev, next, last) \
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do { \
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(prev)->thread.sched_lr = \
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(unsigned long) __builtin_return_address(0); \
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(last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
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mb(); \
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} while(0)
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/*
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* interrupt flag manipulation
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* - use virtual interrupt management since touching the PSR is slow
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* - ICC2.Z: T if interrupts virtually disabled
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* - ICC2.C: F if interrupts really disabled
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* - if Z==1 upon interrupt:
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* - C is set to 0
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* - interrupts are really disabled
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* - entry.S returns immediately
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* - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
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* - if taken, the trap:
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* - sets ICC2.C
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* - enables interrupts
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*/
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#define local_irq_disable() \
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do { \
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/* set Z flag, but don't change the C flag */ \
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asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_irq_enable() \
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do { \
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/* clear Z flag and then test the C flag */ \
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asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
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" tihi icc2,gr0,#2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_save_flags(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm volatile("movsg ccr,%0" \
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: "=r"(flags) \
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: \
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: "memory"); \
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\
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/* shift ICC2.Z to bit 0 */ \
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flags >>= 26; \
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\
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/* make flags 1 if interrupts disabled, 0 otherwise */ \
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flags &= 1UL; \
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} while(0)
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#define irqs_disabled() \
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({unsigned long flags; local_save_flags(flags); flags; })
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#define local_irq_save(flags) \
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do { \
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typecheck(unsigned long, flags); \
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local_save_flags(flags); \
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local_irq_disable(); \
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} while(0)
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#define local_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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\
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/* load the Z flag by turning 1 if disabled into 0 if disabled \
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* and thus setting the Z flag but not the C flag */ \
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asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
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/* then test Z=0 and C=0 */ \
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" tihi icc2,gr0,#2 \n" \
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: \
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: "r"(flags) \
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: "memory", "icc2" \
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); \
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\
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} while(0)
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/*
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* real interrupt flag manipulation
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*/
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#define __local_irq_disable() \
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%2,%0 \n" \
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" ori %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_irq_enable() \
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_save_flags(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm("movsg psr,%0" \
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: "=r"(flags) \
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: \
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: "memory"); \
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} while(0)
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#define __local_irq_save(flags) \
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do { \
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unsigned long npsr; \
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typecheck(unsigned long, flags); \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%3,%1 \n" \
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" ori %1,%2,%1 \n" \
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" movgs %1,psr \n" \
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: "=r"(flags), "=r"(npsr) \
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: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm volatile(" movgs %0,psr \n" \
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: \
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: "r" (flags) \
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: "memory"); \
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} while(0)
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#define __irqs_disabled() \
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((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
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/*
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* Force strict CPU ordering.
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*/
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#define nop() asm volatile ("nop"::)
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#define mb() asm volatile ("membar" : : :"memory")
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#define rmb() asm volatile ("membar" : : :"memory")
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#define wmb() asm volatile ("membar" : : :"memory")
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define read_barrier_depends() do {} while(0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#define HARD_RESET_NOW() \
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do { \
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cli(); \
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} while(1)
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extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
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extern void free_initmem(void);
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#define arch_align_stack(x) (x)
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#endif /* _ASM_SYSTEM_H */
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