mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 01:36:55 +07:00
6fa52ed33b
This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem
specific interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into
platform specific interface, or to get called from platform specific
code, as long as all information about the hardware is provided
through a device tree.
Most of the drivers we touch this time are for clocksource. Since
now most of them are part of drivers/clocksource, I expect that we
won't have to touch these again from arm-soc and can let the
clocksource maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the
merge conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface
for taking devices on the SoC out of reset or back into reset.
Patches to use this interface on i.MX follow later in this merge
window, and we are going to have other platforms (at least tegra
and sirf) get converted in 3.11. This will let us get rid of
platform specific callbacks in a number of platform independent
device drivers.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.
Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
...
1982 lines
51 KiB
C
1982 lines
51 KiB
C
/*
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* On-Chip devices setup code for the AT91SAM9G45 family
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*
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* Copyright (C) 2009 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/i2c-gpio.h>
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#include <linux/atmel-mci.h>
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#include <linux/platform_data/crypto-atmel.h>
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#include <linux/platform_data/at91_adc.h>
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#include <linux/fb.h>
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#include <video/atmel_lcdc.h>
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#include <mach/at91_adc.h>
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#include <mach/at91sam9g45.h>
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#include <mach/at91sam9g45_matrix.h>
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#include <mach/at91_matrix.h>
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#include <mach/at91sam9_smc.h>
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#include <linux/platform_data/dma-atmel.h>
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#include <mach/atmel-mci.h>
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#include <media/atmel-isi.h>
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#include "board.h"
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#include "generic.h"
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#include "clock.h"
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/* --------------------------------------------------------------------
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* HDMAC - AHB DMA Controller
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
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static u64 hdmac_dmamask = DMA_BIT_MASK(32);
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static struct resource hdmac_resources[] = {
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[0] = {
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.start = AT91SAM9G45_BASE_DMA,
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.end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
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.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at_hdmac_device = {
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.name = "at91sam9g45_dma",
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.id = -1,
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.dev = {
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.dma_mask = &hdmac_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = hdmac_resources,
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.num_resources = ARRAY_SIZE(hdmac_resources),
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};
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void __init at91_add_device_hdmac(void)
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{
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platform_device_register(&at_hdmac_device);
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}
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#else
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void __init at91_add_device_hdmac(void) {}
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#endif
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/* --------------------------------------------------------------------
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* USB Host (OHCI)
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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static u64 ohci_dmamask = DMA_BIT_MASK(32);
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static struct at91_usbh_data usbh_ohci_data;
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static struct resource usbh_ohci_resources[] = {
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[0] = {
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.start = AT91SAM9G45_OHCI_BASE,
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.end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
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.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91_usbh_ohci_device = {
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.name = "at91_ohci",
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.id = -1,
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.dev = {
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.dma_mask = &ohci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &usbh_ohci_data,
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},
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.resource = usbh_ohci_resources,
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.num_resources = ARRAY_SIZE(usbh_ohci_resources),
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};
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void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
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{
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int i;
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if (!data)
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return;
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/* Enable VBus control for UHP ports */
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for (i = 0; i < data->ports; i++) {
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if (gpio_is_valid(data->vbus_pin[i]))
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at91_set_gpio_output(data->vbus_pin[i],
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data->vbus_pin_active_low[i]);
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}
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/* Enable overcurrent notification */
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for (i = 0; i < data->ports; i++) {
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if (gpio_is_valid(data->overcurrent_pin[i]))
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at91_set_gpio_input(data->overcurrent_pin[i], 1);
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}
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usbh_ohci_data = *data;
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platform_device_register(&at91_usbh_ohci_device);
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}
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#else
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void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* USB Host HS (EHCI)
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* Needs an OHCI host for low and full speed management
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
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static u64 ehci_dmamask = DMA_BIT_MASK(32);
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static struct at91_usbh_data usbh_ehci_data;
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static struct resource usbh_ehci_resources[] = {
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[0] = {
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.start = AT91SAM9G45_EHCI_BASE,
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.end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
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.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91_usbh_ehci_device = {
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.name = "atmel-ehci",
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.id = -1,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &usbh_ehci_data,
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},
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.resource = usbh_ehci_resources,
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.num_resources = ARRAY_SIZE(usbh_ehci_resources),
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};
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void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
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{
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int i;
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if (!data)
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return;
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/* Enable VBus control for UHP ports */
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for (i = 0; i < data->ports; i++) {
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if (gpio_is_valid(data->vbus_pin[i]))
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at91_set_gpio_output(data->vbus_pin[i],
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data->vbus_pin_active_low[i]);
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}
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usbh_ehci_data = *data;
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platform_device_register(&at91_usbh_ehci_device);
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}
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#else
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void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* USB HS Device (Gadget)
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
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static struct resource usba_udc_resources[] = {
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[0] = {
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.start = AT91SAM9G45_UDPHS_FIFO,
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.end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9G45_BASE_UDPHS,
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.end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
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.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
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.flags = IORESOURCE_IRQ,
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},
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};
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#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
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[idx] = { \
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.name = nam, \
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.index = idx, \
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.fifo_size = maxpkt, \
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.nr_banks = maxbk, \
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.can_dma = dma, \
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.can_isoc = isoc, \
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}
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static struct usba_ep_data usba_udc_ep[] __initdata = {
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EP("ep0", 0, 64, 1, 0, 0),
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EP("ep1", 1, 1024, 2, 1, 1),
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EP("ep2", 2, 1024, 2, 1, 1),
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EP("ep3", 3, 1024, 3, 1, 0),
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EP("ep4", 4, 1024, 3, 1, 0),
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EP("ep5", 5, 1024, 3, 1, 1),
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EP("ep6", 6, 1024, 3, 1, 1),
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};
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#undef EP
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/*
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* pdata doesn't have room for any endpoints, so we need to
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* append room for the ones we need right after it.
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*/
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static struct {
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struct usba_platform_data pdata;
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struct usba_ep_data ep[7];
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} usba_udc_data;
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static struct platform_device at91_usba_udc_device = {
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.name = "atmel_usba_udc",
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.id = -1,
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.dev = {
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.platform_data = &usba_udc_data.pdata,
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},
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.resource = usba_udc_resources,
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.num_resources = ARRAY_SIZE(usba_udc_resources),
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};
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void __init at91_add_device_usba(struct usba_platform_data *data)
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{
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usba_udc_data.pdata.vbus_pin = -EINVAL;
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usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
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memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
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if (data && gpio_is_valid(data->vbus_pin)) {
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at91_set_gpio_input(data->vbus_pin, 0);
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at91_set_deglitch(data->vbus_pin, 1);
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usba_udc_data.pdata.vbus_pin = data->vbus_pin;
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}
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/* Pullup pin is handled internally by USB device peripheral */
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platform_device_register(&at91_usba_udc_device);
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}
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#else
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void __init at91_add_device_usba(struct usba_platform_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* Ethernet
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
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static u64 eth_dmamask = DMA_BIT_MASK(32);
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static struct macb_platform_data eth_data;
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static struct resource eth_resources[] = {
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[0] = {
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.start = AT91SAM9G45_BASE_EMAC,
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.end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
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.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91sam9g45_eth_device = {
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.name = "macb",
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.id = -1,
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.dev = {
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.dma_mask = ð_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = ð_data,
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},
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.resource = eth_resources,
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.num_resources = ARRAY_SIZE(eth_resources),
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};
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void __init at91_add_device_eth(struct macb_platform_data *data)
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{
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if (!data)
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return;
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if (gpio_is_valid(data->phy_irq_pin)) {
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at91_set_gpio_input(data->phy_irq_pin, 0);
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at91_set_deglitch(data->phy_irq_pin, 1);
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}
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/* Pins used for MII and RMII */
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at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
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if (!data->is_rmii) {
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at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
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at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
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at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
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at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
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at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
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at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
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at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
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at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
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}
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eth_data = *data;
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platform_device_register(&at91sam9g45_eth_device);
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}
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#else
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void __init at91_add_device_eth(struct macb_platform_data *data) {}
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#endif
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/* --------------------------------------------------------------------
|
|
* MMC / SD
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
|
|
static u64 mmc_dmamask = DMA_BIT_MASK(32);
|
|
static struct mci_platform_data mmc0_data, mmc1_data;
|
|
|
|
static struct resource mmc0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_MCI0,
|
|
.end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_mmc0_device = {
|
|
.name = "atmel_mci",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &mmc_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &mmc0_data,
|
|
},
|
|
.resource = mmc0_resources,
|
|
.num_resources = ARRAY_SIZE(mmc0_resources),
|
|
};
|
|
|
|
static struct resource mmc1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_MCI1,
|
|
.end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_mmc1_device = {
|
|
.name = "atmel_mci",
|
|
.id = 1,
|
|
.dev = {
|
|
.dma_mask = &mmc_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &mmc1_data,
|
|
},
|
|
.resource = mmc1_resources,
|
|
.num_resources = ARRAY_SIZE(mmc1_resources),
|
|
};
|
|
|
|
/* Consider only one slot : slot 0 */
|
|
void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
|
|
{
|
|
|
|
if (!data)
|
|
return;
|
|
|
|
/* Must have at least one usable slot */
|
|
if (!data->slot[0].bus_width)
|
|
return;
|
|
|
|
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
|
|
{
|
|
struct at_dma_slave *atslave;
|
|
struct mci_dma_data *alt_atslave;
|
|
|
|
alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
|
|
atslave = &alt_atslave->sdata;
|
|
|
|
/* DMA slave channel configuration */
|
|
atslave->dma_dev = &at_hdmac_device.dev;
|
|
atslave->cfg = ATC_FIFOCFG_HALFFIFO
|
|
| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
|
|
if (mmc_id == 0) /* MCI0 */
|
|
atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
|
|
| ATC_DST_PER(AT_DMA_ID_MCI0);
|
|
|
|
else /* MCI1 */
|
|
atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
|
|
| ATC_DST_PER(AT_DMA_ID_MCI1);
|
|
|
|
data->dma_slave = alt_atslave;
|
|
}
|
|
#endif
|
|
|
|
|
|
/* input/irq */
|
|
if (gpio_is_valid(data->slot[0].detect_pin)) {
|
|
at91_set_gpio_input(data->slot[0].detect_pin, 1);
|
|
at91_set_deglitch(data->slot[0].detect_pin, 1);
|
|
}
|
|
if (gpio_is_valid(data->slot[0].wp_pin))
|
|
at91_set_gpio_input(data->slot[0].wp_pin, 1);
|
|
|
|
if (mmc_id == 0) { /* MCI0 */
|
|
|
|
/* CLK */
|
|
at91_set_A_periph(AT91_PIN_PA0, 0);
|
|
|
|
/* CMD */
|
|
at91_set_A_periph(AT91_PIN_PA1, 1);
|
|
|
|
/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
|
|
at91_set_A_periph(AT91_PIN_PA2, 1);
|
|
if (data->slot[0].bus_width == 4) {
|
|
at91_set_A_periph(AT91_PIN_PA3, 1);
|
|
at91_set_A_periph(AT91_PIN_PA4, 1);
|
|
at91_set_A_periph(AT91_PIN_PA5, 1);
|
|
if (data->slot[0].bus_width == 8) {
|
|
at91_set_A_periph(AT91_PIN_PA6, 1);
|
|
at91_set_A_periph(AT91_PIN_PA7, 1);
|
|
at91_set_A_periph(AT91_PIN_PA8, 1);
|
|
at91_set_A_periph(AT91_PIN_PA9, 1);
|
|
}
|
|
}
|
|
|
|
mmc0_data = *data;
|
|
platform_device_register(&at91sam9g45_mmc0_device);
|
|
|
|
} else { /* MCI1 */
|
|
|
|
/* CLK */
|
|
at91_set_A_periph(AT91_PIN_PA31, 0);
|
|
|
|
/* CMD */
|
|
at91_set_A_periph(AT91_PIN_PA22, 1);
|
|
|
|
/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
|
|
at91_set_A_periph(AT91_PIN_PA23, 1);
|
|
if (data->slot[0].bus_width == 4) {
|
|
at91_set_A_periph(AT91_PIN_PA24, 1);
|
|
at91_set_A_periph(AT91_PIN_PA25, 1);
|
|
at91_set_A_periph(AT91_PIN_PA26, 1);
|
|
if (data->slot[0].bus_width == 8) {
|
|
at91_set_A_periph(AT91_PIN_PA27, 1);
|
|
at91_set_A_periph(AT91_PIN_PA28, 1);
|
|
at91_set_A_periph(AT91_PIN_PA29, 1);
|
|
at91_set_A_periph(AT91_PIN_PA30, 1);
|
|
}
|
|
}
|
|
|
|
mmc1_data = *data;
|
|
platform_device_register(&at91sam9g45_mmc1_device);
|
|
|
|
}
|
|
}
|
|
#else
|
|
void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* NAND / SmartMedia
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
|
|
static struct atmel_nand_data nand_data;
|
|
|
|
#define NAND_BASE AT91_CHIPSELECT_3
|
|
|
|
static struct resource nand_resources[] = {
|
|
[0] = {
|
|
.start = NAND_BASE,
|
|
.end = NAND_BASE + SZ_256M - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = AT91SAM9G45_BASE_ECC,
|
|
.end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_nand_device = {
|
|
.name = "atmel_nand",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &nand_data,
|
|
},
|
|
.resource = nand_resources,
|
|
.num_resources = ARRAY_SIZE(nand_resources),
|
|
};
|
|
|
|
void __init at91_add_device_nand(struct atmel_nand_data *data)
|
|
{
|
|
unsigned long csa;
|
|
|
|
if (!data)
|
|
return;
|
|
|
|
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
|
|
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
|
|
|
|
/* enable pin */
|
|
if (gpio_is_valid(data->enable_pin))
|
|
at91_set_gpio_output(data->enable_pin, 1);
|
|
|
|
/* ready/busy pin */
|
|
if (gpio_is_valid(data->rdy_pin))
|
|
at91_set_gpio_input(data->rdy_pin, 1);
|
|
|
|
/* card detect pin */
|
|
if (gpio_is_valid(data->det_pin))
|
|
at91_set_gpio_input(data->det_pin, 1);
|
|
|
|
nand_data = *data;
|
|
platform_device_register(&at91sam9g45_nand_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* TWI (i2c)
|
|
* -------------------------------------------------------------------- */
|
|
|
|
/*
|
|
* Prefer the GPIO code since the TWI controller isn't robust
|
|
* (gets overruns and underruns under load) and can only issue
|
|
* repeated STARTs in one scenario (the driver doesn't yet handle them).
|
|
*/
|
|
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
|
|
static struct i2c_gpio_platform_data pdata_i2c0 = {
|
|
.sda_pin = AT91_PIN_PA20,
|
|
.sda_is_open_drain = 1,
|
|
.scl_pin = AT91_PIN_PA21,
|
|
.scl_is_open_drain = 1,
|
|
.udelay = 5, /* ~100 kHz */
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_twi0_device = {
|
|
.name = "i2c-gpio",
|
|
.id = 0,
|
|
.dev.platform_data = &pdata_i2c0,
|
|
};
|
|
|
|
static struct i2c_gpio_platform_data pdata_i2c1 = {
|
|
.sda_pin = AT91_PIN_PB10,
|
|
.sda_is_open_drain = 1,
|
|
.scl_pin = AT91_PIN_PB11,
|
|
.scl_is_open_drain = 1,
|
|
.udelay = 5, /* ~100 kHz */
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_twi1_device = {
|
|
.name = "i2c-gpio",
|
|
.id = 1,
|
|
.dev.platform_data = &pdata_i2c1,
|
|
};
|
|
|
|
void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
|
|
{
|
|
i2c_register_board_info(i2c_id, devices, nr_devices);
|
|
|
|
if (i2c_id == 0) {
|
|
at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
|
|
at91_set_multi_drive(AT91_PIN_PA20, 1);
|
|
|
|
at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
|
|
at91_set_multi_drive(AT91_PIN_PA21, 1);
|
|
|
|
platform_device_register(&at91sam9g45_twi0_device);
|
|
} else {
|
|
at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
|
|
at91_set_multi_drive(AT91_PIN_PB10, 1);
|
|
|
|
at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
|
|
at91_set_multi_drive(AT91_PIN_PB11, 1);
|
|
|
|
platform_device_register(&at91sam9g45_twi1_device);
|
|
}
|
|
}
|
|
|
|
#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
|
|
static struct resource twi0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TWI0,
|
|
.end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_twi0_device = {
|
|
.name = "i2c-at91sam9g10",
|
|
.id = 0,
|
|
.resource = twi0_resources,
|
|
.num_resources = ARRAY_SIZE(twi0_resources),
|
|
};
|
|
|
|
static struct resource twi1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TWI1,
|
|
.end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_twi1_device = {
|
|
.name = "i2c-at91sam9g10",
|
|
.id = 1,
|
|
.resource = twi1_resources,
|
|
.num_resources = ARRAY_SIZE(twi1_resources),
|
|
};
|
|
|
|
void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
|
|
{
|
|
i2c_register_board_info(i2c_id, devices, nr_devices);
|
|
|
|
/* pins used for TWI interface */
|
|
if (i2c_id == 0) {
|
|
at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
|
|
at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
|
|
|
|
platform_device_register(&at91sam9g45_twi0_device);
|
|
} else {
|
|
at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
|
|
at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
|
|
|
|
platform_device_register(&at91sam9g45_twi1_device);
|
|
}
|
|
}
|
|
#else
|
|
void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* SPI
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
|
|
static u64 spi_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct resource spi0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_SPI0,
|
|
.end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_spi0_device = {
|
|
.name = "atmel_spi",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &spi_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.resource = spi0_resources,
|
|
.num_resources = ARRAY_SIZE(spi0_resources),
|
|
};
|
|
|
|
static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
|
|
|
|
static struct resource spi1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_SPI1,
|
|
.end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_spi1_device = {
|
|
.name = "atmel_spi",
|
|
.id = 1,
|
|
.dev = {
|
|
.dma_mask = &spi_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.resource = spi1_resources,
|
|
.num_resources = ARRAY_SIZE(spi1_resources),
|
|
};
|
|
|
|
static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
|
|
|
|
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
|
|
{
|
|
int i;
|
|
unsigned long cs_pin;
|
|
short enable_spi0 = 0;
|
|
short enable_spi1 = 0;
|
|
|
|
/* Choose SPI chip-selects */
|
|
for (i = 0; i < nr_devices; i++) {
|
|
if (devices[i].controller_data)
|
|
cs_pin = (unsigned long) devices[i].controller_data;
|
|
else if (devices[i].bus_num == 0)
|
|
cs_pin = spi0_standard_cs[devices[i].chip_select];
|
|
else
|
|
cs_pin = spi1_standard_cs[devices[i].chip_select];
|
|
|
|
if (!gpio_is_valid(cs_pin))
|
|
continue;
|
|
|
|
if (devices[i].bus_num == 0)
|
|
enable_spi0 = 1;
|
|
else
|
|
enable_spi1 = 1;
|
|
|
|
/* enable chip-select pin */
|
|
at91_set_gpio_output(cs_pin, 1);
|
|
|
|
/* pass chip-select pin to driver */
|
|
devices[i].controller_data = (void *) cs_pin;
|
|
}
|
|
|
|
spi_register_board_info(devices, nr_devices);
|
|
|
|
/* Configure SPI bus(es) */
|
|
if (enable_spi0) {
|
|
at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
|
|
at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
|
|
at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
|
|
|
|
platform_device_register(&at91sam9g45_spi0_device);
|
|
}
|
|
if (enable_spi1) {
|
|
at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
|
|
at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
|
|
at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
|
|
|
|
platform_device_register(&at91sam9g45_spi1_device);
|
|
}
|
|
}
|
|
#else
|
|
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* AC97
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
|
|
static u64 ac97_dmamask = DMA_BIT_MASK(32);
|
|
static struct ac97c_platform_data ac97_data;
|
|
|
|
static struct resource ac97_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_AC97C,
|
|
.end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_ac97_device = {
|
|
.name = "atmel_ac97c",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &ac97_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &ac97_data,
|
|
},
|
|
.resource = ac97_resources,
|
|
.num_resources = ARRAY_SIZE(ac97_resources),
|
|
};
|
|
|
|
void __init at91_add_device_ac97(struct ac97c_platform_data *data)
|
|
{
|
|
if (!data)
|
|
return;
|
|
|
|
at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
|
|
at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
|
|
at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
|
|
at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
|
|
|
|
/* reset */
|
|
if (gpio_is_valid(data->reset_pin))
|
|
at91_set_gpio_output(data->reset_pin, 0);
|
|
|
|
ac97_data = *data;
|
|
platform_device_register(&at91sam9g45_ac97_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* Image Sensor Interface
|
|
* -------------------------------------------------------------------- */
|
|
#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
|
|
static u64 isi_dmamask = DMA_BIT_MASK(32);
|
|
static struct isi_platform_data isi_data;
|
|
|
|
struct resource isi_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_ISI,
|
|
.end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_isi_device = {
|
|
.name = "atmel_isi",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &isi_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &isi_data,
|
|
},
|
|
.resource = isi_resources,
|
|
.num_resources = ARRAY_SIZE(isi_resources),
|
|
};
|
|
|
|
static struct clk_lookup isi_mck_lookups[] = {
|
|
CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
|
|
};
|
|
|
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
|
bool use_pck_as_mck)
|
|
{
|
|
struct clk *pck;
|
|
struct clk *parent;
|
|
|
|
if (!data)
|
|
return;
|
|
isi_data = *data;
|
|
|
|
at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
|
|
at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
|
|
at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
|
|
at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
|
|
at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
|
|
at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
|
|
at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
|
|
at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
|
|
at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
|
|
at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
|
|
at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
|
|
at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
|
|
at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
|
|
at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
|
|
at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
|
|
|
|
platform_device_register(&at91sam9g45_isi_device);
|
|
|
|
if (use_pck_as_mck) {
|
|
at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
|
|
|
|
pck = clk_get(NULL, "pck1");
|
|
parent = clk_get(NULL, "plla");
|
|
|
|
BUG_ON(IS_ERR(pck) || IS_ERR(parent));
|
|
|
|
if (clk_set_parent(pck, parent)) {
|
|
pr_err("Failed to set PCK's parent\n");
|
|
} else {
|
|
/* Register PCK as ISI_MCK */
|
|
isi_mck_lookups[0].clk = pck;
|
|
clkdev_add_table(isi_mck_lookups,
|
|
ARRAY_SIZE(isi_mck_lookups));
|
|
}
|
|
|
|
clk_put(pck);
|
|
clk_put(parent);
|
|
}
|
|
}
|
|
#else
|
|
void __init at91_add_device_isi(struct isi_platform_data *data,
|
|
bool use_pck_as_mck) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* LCD Controller
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
|
|
static u64 lcdc_dmamask = DMA_BIT_MASK(32);
|
|
static struct atmel_lcdfb_info lcdc_data;
|
|
|
|
static struct resource lcdc_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_LCDC_BASE,
|
|
.end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91_lcdc_device = {
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &lcdc_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &lcdc_data,
|
|
},
|
|
.resource = lcdc_resources,
|
|
.num_resources = ARRAY_SIZE(lcdc_resources),
|
|
};
|
|
|
|
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
|
{
|
|
if (!data)
|
|
return;
|
|
|
|
if (cpu_is_at91sam9g45es())
|
|
at91_lcdc_device.name = "at91sam9g45es-lcdfb";
|
|
else
|
|
at91_lcdc_device.name = "at91sam9g45-lcdfb";
|
|
|
|
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
|
|
|
|
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
|
|
at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
|
|
at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
|
|
at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
|
|
at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
|
|
at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
|
|
at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
|
|
at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
|
|
at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
|
|
at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
|
|
at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
|
|
at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
|
|
at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
|
|
at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
|
|
at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
|
|
at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
|
|
at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
|
|
at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
|
|
at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
|
|
at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
|
|
at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
|
|
at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
|
|
at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
|
|
at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
|
|
at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
|
|
at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
|
|
at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
|
|
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
|
|
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
|
|
|
|
lcdc_data = *data;
|
|
platform_device_register(&at91_lcdc_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* Timer/Counter block
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#ifdef CONFIG_ATMEL_TCLIB
|
|
static struct resource tcb0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TCB0,
|
|
.end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_tcb0_device = {
|
|
.name = "atmel_tcb",
|
|
.id = 0,
|
|
.resource = tcb0_resources,
|
|
.num_resources = ARRAY_SIZE(tcb0_resources),
|
|
};
|
|
|
|
/* TCB1 begins with TC3 */
|
|
static struct resource tcb1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TCB1,
|
|
.end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_tcb1_device = {
|
|
.name = "atmel_tcb",
|
|
.id = 1,
|
|
.resource = tcb1_resources,
|
|
.num_resources = ARRAY_SIZE(tcb1_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_tc(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_tcb0_device);
|
|
platform_device_register(&at91sam9g45_tcb1_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_tc(void) { }
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* RTC
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
|
|
static struct resource rtc_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_RTC,
|
|
.end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91_ID_SYS,
|
|
.end = NR_IRQS_LEGACY + AT91_ID_SYS,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_rtc_device = {
|
|
.name = "at91_rtc",
|
|
.id = -1,
|
|
.resource = rtc_resources,
|
|
.num_resources = ARRAY_SIZE(rtc_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_rtc(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_rtc_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_rtc(void) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* Touchscreen
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
|
|
static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
|
|
static struct at91_tsadcc_data tsadcc_data;
|
|
|
|
static struct resource tsadcc_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TSC,
|
|
.end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_tsadcc_device = {
|
|
.name = "atmel_tsadcc",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &tsadcc_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &tsadcc_data,
|
|
},
|
|
.resource = tsadcc_resources,
|
|
.num_resources = ARRAY_SIZE(tsadcc_resources),
|
|
};
|
|
|
|
void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
|
|
{
|
|
if (!data)
|
|
return;
|
|
|
|
at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
|
|
at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
|
|
at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
|
|
at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
|
|
|
|
tsadcc_data = *data;
|
|
platform_device_register(&at91sam9g45_tsadcc_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* ADC
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if IS_ENABLED(CONFIG_AT91_ADC)
|
|
static struct at91_adc_data adc_data;
|
|
|
|
static struct resource adc_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TSC,
|
|
.end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
|
|
static struct platform_device at91_adc_device = {
|
|
.name = "at91_adc",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &adc_data,
|
|
},
|
|
.resource = adc_resources,
|
|
.num_resources = ARRAY_SIZE(adc_resources),
|
|
};
|
|
|
|
static struct at91_adc_trigger at91_adc_triggers[] = {
|
|
[0] = {
|
|
.name = "external-rising",
|
|
.value = 1,
|
|
.is_external = true,
|
|
},
|
|
[1] = {
|
|
.name = "external-falling",
|
|
.value = 2,
|
|
.is_external = true,
|
|
},
|
|
[2] = {
|
|
.name = "external-any",
|
|
.value = 3,
|
|
.is_external = true,
|
|
},
|
|
[3] = {
|
|
.name = "continuous",
|
|
.value = 6,
|
|
.is_external = false,
|
|
},
|
|
};
|
|
|
|
static struct at91_adc_reg_desc at91_adc_register_g45 = {
|
|
.channel_base = AT91_ADC_CHR(0),
|
|
.drdy_mask = AT91_ADC_DRDY,
|
|
.status_register = AT91_ADC_SR,
|
|
.trigger_register = 0x08,
|
|
};
|
|
|
|
void __init at91_add_device_adc(struct at91_adc_data *data)
|
|
{
|
|
if (!data)
|
|
return;
|
|
|
|
if (test_bit(0, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD20, 0);
|
|
if (test_bit(1, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD21, 0);
|
|
if (test_bit(2, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD22, 0);
|
|
if (test_bit(3, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD23, 0);
|
|
if (test_bit(4, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD24, 0);
|
|
if (test_bit(5, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD25, 0);
|
|
if (test_bit(6, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD26, 0);
|
|
if (test_bit(7, &data->channels_used))
|
|
at91_set_gpio_input(AT91_PIN_PD27, 0);
|
|
|
|
if (data->use_external_triggers)
|
|
at91_set_A_periph(AT91_PIN_PD28, 0);
|
|
|
|
data->num_channels = 8;
|
|
data->startup_time = 40;
|
|
data->registers = &at91_adc_register_g45;
|
|
data->trigger_number = 4;
|
|
data->trigger_list = at91_adc_triggers;
|
|
|
|
adc_data = *data;
|
|
platform_device_register(&at91_adc_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_adc(struct at91_adc_data *data) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* RTT
|
|
* -------------------------------------------------------------------- */
|
|
|
|
static struct resource rtt_resources[] = {
|
|
{
|
|
.start = AT91SAM9G45_BASE_RTT,
|
|
.end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_rtt_device = {
|
|
.name = "at91_rtt",
|
|
.id = 0,
|
|
.resource = rtt_resources,
|
|
};
|
|
|
|
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
|
|
static void __init at91_add_device_rtt_rtc(void)
|
|
{
|
|
at91sam9g45_rtt_device.name = "rtc-at91sam9";
|
|
/*
|
|
* The second resource is needed:
|
|
* GPBR will serve as the storage for RTC time offset
|
|
*/
|
|
at91sam9g45_rtt_device.num_resources = 3;
|
|
rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
|
|
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
|
rtt_resources[1].end = rtt_resources[1].start + 3;
|
|
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
|
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
|
}
|
|
#else
|
|
static void __init at91_add_device_rtt_rtc(void)
|
|
{
|
|
/* Only one resource is needed: RTT not used as RTC */
|
|
at91sam9g45_rtt_device.num_resources = 1;
|
|
}
|
|
#endif
|
|
|
|
static void __init at91_add_device_rtt(void)
|
|
{
|
|
at91_add_device_rtt_rtc();
|
|
platform_device_register(&at91sam9g45_rtt_device);
|
|
}
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* TRNG
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
|
|
static struct resource trng_resources[] = {
|
|
{
|
|
.start = AT91SAM9G45_BASE_TRNG,
|
|
.end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_trng_device = {
|
|
.name = "atmel-trng",
|
|
.id = -1,
|
|
.resource = trng_resources,
|
|
.num_resources = ARRAY_SIZE(trng_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_trng(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_trng_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_trng(void) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* Watchdog
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
|
|
static struct resource wdt_resources[] = {
|
|
{
|
|
.start = AT91SAM9G45_BASE_WDT,
|
|
.end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_wdt_device = {
|
|
.name = "at91_wdt",
|
|
.id = -1,
|
|
.resource = wdt_resources,
|
|
.num_resources = ARRAY_SIZE(wdt_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_watchdog(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_wdt_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_watchdog(void) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* PWM
|
|
* --------------------------------------------------------------------*/
|
|
|
|
#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
|
|
static u32 pwm_mask;
|
|
|
|
static struct resource pwm_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_PWMC,
|
|
.end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_pwm0_device = {
|
|
.name = "atmel_pwm",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &pwm_mask,
|
|
},
|
|
.resource = pwm_resources,
|
|
.num_resources = ARRAY_SIZE(pwm_resources),
|
|
};
|
|
|
|
void __init at91_add_device_pwm(u32 mask)
|
|
{
|
|
if (mask & (1 << AT91_PWM0))
|
|
at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
|
|
|
|
if (mask & (1 << AT91_PWM1))
|
|
at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
|
|
|
|
if (mask & (1 << AT91_PWM2))
|
|
at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
|
|
|
|
if (mask & (1 << AT91_PWM3))
|
|
at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
|
|
|
|
pwm_mask = mask;
|
|
|
|
platform_device_register(&at91sam9g45_pwm0_device);
|
|
}
|
|
#else
|
|
void __init at91_add_device_pwm(u32 mask) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* SSC -- Synchronous Serial Controller
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
|
|
static u64 ssc0_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct resource ssc0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_SSC0,
|
|
.end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_ssc0_device = {
|
|
.name = "at91sam9g45_ssc",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &ssc0_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.resource = ssc0_resources,
|
|
.num_resources = ARRAY_SIZE(ssc0_resources),
|
|
};
|
|
|
|
static inline void configure_ssc0_pins(unsigned pins)
|
|
{
|
|
if (pins & ATMEL_SSC_TF)
|
|
at91_set_A_periph(AT91_PIN_PD1, 1);
|
|
if (pins & ATMEL_SSC_TK)
|
|
at91_set_A_periph(AT91_PIN_PD0, 1);
|
|
if (pins & ATMEL_SSC_TD)
|
|
at91_set_A_periph(AT91_PIN_PD2, 1);
|
|
if (pins & ATMEL_SSC_RD)
|
|
at91_set_A_periph(AT91_PIN_PD3, 1);
|
|
if (pins & ATMEL_SSC_RK)
|
|
at91_set_A_periph(AT91_PIN_PD4, 1);
|
|
if (pins & ATMEL_SSC_RF)
|
|
at91_set_A_periph(AT91_PIN_PD5, 1);
|
|
}
|
|
|
|
static u64 ssc1_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct resource ssc1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_SSC1,
|
|
.end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_ssc1_device = {
|
|
.name = "at91sam9g45_ssc",
|
|
.id = 1,
|
|
.dev = {
|
|
.dma_mask = &ssc1_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.resource = ssc1_resources,
|
|
.num_resources = ARRAY_SIZE(ssc1_resources),
|
|
};
|
|
|
|
static inline void configure_ssc1_pins(unsigned pins)
|
|
{
|
|
if (pins & ATMEL_SSC_TF)
|
|
at91_set_A_periph(AT91_PIN_PD14, 1);
|
|
if (pins & ATMEL_SSC_TK)
|
|
at91_set_A_periph(AT91_PIN_PD12, 1);
|
|
if (pins & ATMEL_SSC_TD)
|
|
at91_set_A_periph(AT91_PIN_PD10, 1);
|
|
if (pins & ATMEL_SSC_RD)
|
|
at91_set_A_periph(AT91_PIN_PD11, 1);
|
|
if (pins & ATMEL_SSC_RK)
|
|
at91_set_A_periph(AT91_PIN_PD13, 1);
|
|
if (pins & ATMEL_SSC_RF)
|
|
at91_set_A_periph(AT91_PIN_PD15, 1);
|
|
}
|
|
|
|
/*
|
|
* SSC controllers are accessed through library code, instead of any
|
|
* kind of all-singing/all-dancing driver. For example one could be
|
|
* used by a particular I2S audio codec's driver, while another one
|
|
* on the same system might be used by a custom data capture driver.
|
|
*/
|
|
void __init at91_add_device_ssc(unsigned id, unsigned pins)
|
|
{
|
|
struct platform_device *pdev;
|
|
|
|
/*
|
|
* NOTE: caller is responsible for passing information matching
|
|
* "pins" to whatever will be using each particular controller.
|
|
*/
|
|
switch (id) {
|
|
case AT91SAM9G45_ID_SSC0:
|
|
pdev = &at91sam9g45_ssc0_device;
|
|
configure_ssc0_pins(pins);
|
|
break;
|
|
case AT91SAM9G45_ID_SSC1:
|
|
pdev = &at91sam9g45_ssc1_device;
|
|
configure_ssc1_pins(pins);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
platform_device_register(pdev);
|
|
}
|
|
|
|
#else
|
|
void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
|
|
#endif
|
|
|
|
|
|
/* --------------------------------------------------------------------
|
|
* UART
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_SERIAL_ATMEL)
|
|
static struct resource dbgu_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_DBGU,
|
|
.end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91_ID_SYS,
|
|
.end = NR_IRQS_LEGACY + AT91_ID_SYS,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct atmel_uart_data dbgu_data = {
|
|
.use_dma_tx = 0,
|
|
.use_dma_rx = 0,
|
|
};
|
|
|
|
static u64 dbgu_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device at91sam9g45_dbgu_device = {
|
|
.name = "atmel_usart",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &dbgu_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &dbgu_data,
|
|
},
|
|
.resource = dbgu_resources,
|
|
.num_resources = ARRAY_SIZE(dbgu_resources),
|
|
};
|
|
|
|
static inline void configure_dbgu_pins(void)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
|
|
at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
|
|
}
|
|
|
|
static struct resource uart0_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_US0,
|
|
.end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct atmel_uart_data uart0_data = {
|
|
.use_dma_tx = 1,
|
|
.use_dma_rx = 1,
|
|
};
|
|
|
|
static u64 uart0_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device at91sam9g45_uart0_device = {
|
|
.name = "atmel_usart",
|
|
.id = 1,
|
|
.dev = {
|
|
.dma_mask = &uart0_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &uart0_data,
|
|
},
|
|
.resource = uart0_resources,
|
|
.num_resources = ARRAY_SIZE(uart0_resources),
|
|
};
|
|
|
|
static inline void configure_usart0_pins(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
|
|
at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
|
|
}
|
|
|
|
static struct resource uart1_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_US1,
|
|
.end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct atmel_uart_data uart1_data = {
|
|
.use_dma_tx = 1,
|
|
.use_dma_rx = 1,
|
|
};
|
|
|
|
static u64 uart1_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device at91sam9g45_uart1_device = {
|
|
.name = "atmel_usart",
|
|
.id = 2,
|
|
.dev = {
|
|
.dma_mask = &uart1_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &uart1_data,
|
|
},
|
|
.resource = uart1_resources,
|
|
.num_resources = ARRAY_SIZE(uart1_resources),
|
|
};
|
|
|
|
static inline void configure_usart1_pins(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
|
|
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
|
|
}
|
|
|
|
static struct resource uart2_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_US2,
|
|
.end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct atmel_uart_data uart2_data = {
|
|
.use_dma_tx = 1,
|
|
.use_dma_rx = 1,
|
|
};
|
|
|
|
static u64 uart2_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device at91sam9g45_uart2_device = {
|
|
.name = "atmel_usart",
|
|
.id = 3,
|
|
.dev = {
|
|
.dma_mask = &uart2_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &uart2_data,
|
|
},
|
|
.resource = uart2_resources,
|
|
.num_resources = ARRAY_SIZE(uart2_resources),
|
|
};
|
|
|
|
static inline void configure_usart2_pins(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
|
|
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
|
|
}
|
|
|
|
static struct resource uart3_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_US3,
|
|
.end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct atmel_uart_data uart3_data = {
|
|
.use_dma_tx = 1,
|
|
.use_dma_rx = 1,
|
|
};
|
|
|
|
static u64 uart3_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device at91sam9g45_uart3_device = {
|
|
.name = "atmel_usart",
|
|
.id = 4,
|
|
.dev = {
|
|
.dma_mask = &uart3_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &uart3_data,
|
|
},
|
|
.resource = uart3_resources,
|
|
.num_resources = ARRAY_SIZE(uart3_resources),
|
|
};
|
|
|
|
static inline void configure_usart3_pins(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
|
|
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
|
|
}
|
|
|
|
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
|
|
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
|
|
{
|
|
struct platform_device *pdev;
|
|
struct atmel_uart_data *pdata;
|
|
|
|
switch (id) {
|
|
case 0: /* DBGU */
|
|
pdev = &at91sam9g45_dbgu_device;
|
|
configure_dbgu_pins();
|
|
break;
|
|
case AT91SAM9G45_ID_US0:
|
|
pdev = &at91sam9g45_uart0_device;
|
|
configure_usart0_pins(pins);
|
|
break;
|
|
case AT91SAM9G45_ID_US1:
|
|
pdev = &at91sam9g45_uart1_device;
|
|
configure_usart1_pins(pins);
|
|
break;
|
|
case AT91SAM9G45_ID_US2:
|
|
pdev = &at91sam9g45_uart2_device;
|
|
configure_usart2_pins(pins);
|
|
break;
|
|
case AT91SAM9G45_ID_US3:
|
|
pdev = &at91sam9g45_uart3_device;
|
|
configure_usart3_pins(pins);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
pdata = pdev->dev.platform_data;
|
|
pdata->num = portnr; /* update to mapped ID */
|
|
|
|
if (portnr < ATMEL_MAX_UART)
|
|
at91_uarts[portnr] = pdev;
|
|
}
|
|
|
|
void __init at91_add_device_serial(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ATMEL_MAX_UART; i++) {
|
|
if (at91_uarts[i])
|
|
platform_device_register(at91_uarts[i]);
|
|
}
|
|
}
|
|
#else
|
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
|
void __init at91_add_device_serial(void) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* SHA1/SHA256
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
|
|
static struct resource sha_resources[] = {
|
|
{
|
|
.start = AT91SAM9G45_BASE_SHA,
|
|
.end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_sha_device = {
|
|
.name = "atmel_sha",
|
|
.id = -1,
|
|
.resource = sha_resources,
|
|
.num_resources = ARRAY_SIZE(sha_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_sha(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_sha_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_sha(void) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* DES/TDES
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
|
|
static struct resource tdes_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_TDES,
|
|
.end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_tdes_device = {
|
|
.name = "atmel_tdes",
|
|
.id = -1,
|
|
.resource = tdes_resources,
|
|
.num_resources = ARRAY_SIZE(tdes_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_tdes(void)
|
|
{
|
|
platform_device_register(&at91sam9g45_tdes_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_tdes(void) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* AES
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
|
|
static struct crypto_platform_data aes_data;
|
|
static struct crypto_dma_data alt_atslave;
|
|
static u64 aes_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct resource aes_resources[] = {
|
|
[0] = {
|
|
.start = AT91SAM9G45_BASE_AES,
|
|
.end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device at91sam9g45_aes_device = {
|
|
.name = "atmel_aes",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &aes_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &aes_data,
|
|
},
|
|
.resource = aes_resources,
|
|
.num_resources = ARRAY_SIZE(aes_resources),
|
|
};
|
|
|
|
static void __init at91_add_device_aes(void)
|
|
{
|
|
struct at_dma_slave *atslave;
|
|
|
|
/* DMA TX slave channel configuration */
|
|
atslave = &alt_atslave.txdata;
|
|
atslave->dma_dev = &at_hdmac_device.dev;
|
|
atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
|
|
ATC_SRC_PER(AT_DMA_ID_AES_RX);
|
|
|
|
/* DMA RX slave channel configuration */
|
|
atslave = &alt_atslave.rxdata;
|
|
atslave->dma_dev = &at_hdmac_device.dev;
|
|
atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
|
|
ATC_DST_PER(AT_DMA_ID_AES_TX);
|
|
|
|
aes_data.dma_slave = &alt_atslave;
|
|
platform_device_register(&at91sam9g45_aes_device);
|
|
}
|
|
#else
|
|
static void __init at91_add_device_aes(void) {}
|
|
#endif
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/*
|
|
* These devices are always present and don't need any board-specific
|
|
* setup.
|
|
*/
|
|
static int __init at91_add_standard_devices(void)
|
|
{
|
|
if (of_have_populated_dt())
|
|
return 0;
|
|
|
|
at91_add_device_hdmac();
|
|
at91_add_device_rtc();
|
|
at91_add_device_rtt();
|
|
at91_add_device_trng();
|
|
at91_add_device_watchdog();
|
|
at91_add_device_tc();
|
|
at91_add_device_sha();
|
|
at91_add_device_tdes();
|
|
at91_add_device_aes();
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(at91_add_standard_devices);
|