Mike Turquette bddbd13453 arm: Xilinx Zynq clock changes for v3.12 ... Just small two changes where the first fixes documentation and the second improves code readability. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlITEOUACgkQykllyylKDCF/NACeL44IBsj0MLhdhJmPCZKbt6Iq wIMAn1jLwzIUnKug6TuT3GzsNnrrNaCi =1u+P -----END PGP SIGNATURE----- Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-next arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.		2013-08-20 14:58:48 -07:00
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clkc.c	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	arm: zynq: Migrate platform to clock controller	2013-05-27 09:21:22 +02:00
pll.c	clk/zynq/pll: Use #defines for fbdiv min/max values	2013-08-20 07:54:41 +02:00