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0409d756d0
The Moxa ART GPIO is a Faraday FTGPIO010. Augment the DTS node to indicate both compatible values for the SoC and the IP part. Also increase the register range to 0x100, it has at least 0x48 bytes of registers, and a few extra will not hurt. Tested-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
150 lines
3.1 KiB
Plaintext
150 lines
3.1 KiB
Plaintext
/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
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*
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* Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "moxa,moxart";
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model = "MOXART";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "faraday,fa526";
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reg = <0>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x90000000 0x10000000>;
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ranges;
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intc: interrupt-controller@98800000 {
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compatible = "moxa,moxart-ic", "faraday,ftintc010";
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reg = <0x98800000 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-mask = <0x00080000>;
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};
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clk_pll: clk_pll@98100000 {
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compatible = "moxa,moxart-pll-clock";
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#clock-cells = <0>;
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reg = <0x98100000 0x34>;
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};
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clk_apb: clk_apb@98100000 {
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compatible = "moxa,moxart-apb-clock";
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#clock-cells = <0>;
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reg = <0x98100000 0x34>;
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clocks = <&clk_pll>;
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};
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timer: timer@98400000 {
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compatible = "moxa,moxart-timer";
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reg = <0x98400000 0x42>;
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interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
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clocks = <&clk_apb>;
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};
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gpio: gpio@98700000 {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "moxa,moxart-gpio", "faraday,ftgpio010";
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reg = <0x98700000 0x100>;
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};
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rtc: rtc {
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compatible = "moxa,moxart-rtc";
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gpio-rtc-sclk = <&gpio 5 0>;
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gpio-rtc-data = <&gpio 6 0>;
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gpio-rtc-reset = <&gpio 7 0>;
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};
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dma: dma@90500000 {
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compatible = "moxa,moxart-dma";
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reg = <0x90500080 0x40>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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};
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watchdog: watchdog@98500000 {
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compatible = "moxa,moxart-watchdog";
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reg = <0x98500000 0x10>;
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clocks = <&clk_apb>;
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};
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sdhci: sdhci@98e00000 {
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compatible = "moxa,moxart-sdhci";
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reg = <0x98e00000 0x5C>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_apb>;
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dmas = <&dma 5>,
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<&dma 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mdio0: mdio@90900090 {
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compatible = "moxa,moxart-mdio";
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reg = <0x90900090 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mdio1: mdio@92000090 {
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compatible = "moxa,moxart-mdio";
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reg = <0x92000090 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mac0: mac@90900000 {
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compatible = "moxa,moxart-mac";
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reg = <0x90900000 0x90>;
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interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
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phy-handle = <ðphy0>;
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phy-mode = "mii";
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status = "disabled";
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};
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mac1: mac@92000000 {
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compatible = "moxa,moxart-mac";
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reg = <0x92000000 0x90>;
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interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
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phy-handle = <ðphy1>;
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phy-mode = "mii";
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status = "disabled";
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};
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uart0: uart@98200000 {
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compatible = "ns16550a";
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reg = <0x98200000 0x20>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <14745600>;
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status = "disabled";
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};
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};
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};
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