mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 11:46:54 +07:00
e3037485c6
This is a new mac80211 driver for Realtek 802.11ac wireless network chips. rtw88 now supports RTL8822BE/RTL8822CE now, with basic station mode functionalities. The firmware for both can be found at linux-firmware. https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git For RTL8822BE: rtw88/rtw8822b_fw.bin For RTL8822CE: rtw88/rtw8822c_fw.bin And for now, only PCI buses (RTL8xxxE) are supported. We will add support for USB and SDIO in the future. The bus interface abstraction can be seen in this driver such as hci.h. Most of the hardware setting are the same except for some TRX path or probing setup should be separated. Supported: * Basic STA/AP/ADHOC mode, and TDLS (STA is well tested) Missing feature: * WOW/PNO * USB & SDIO bus (such as RTL8xxxU/RTL8xxxS) * BT coexistence (8822B/8822C are combo ICs) * Multiple interfaces (for now single STA is better supported) * Dynamic hardware calibrations (to improve/stabilize performance) Potential problems: * static calibration spends too much time, and it is painful for driver to leave IDLE state. And slows down associate process. But reload function are under development, will be added soon! * TRX statictics misleading, as we are not reporting status correctly, or say, not reporting for "every" packet. The next patch set should have BT coexistence code since RTL8822B/C are combo ICs, and the driver for BT can be found after Linux Kernel v4.20. So it is better to add it first to make WiFi + BT work concurrently. Although now rtw88 is simple but we are developing more features for it. Even we want to add support for more chips such as RTL8821C/RTL8814B. Finally, rtw88 has many authors, listed alphabetically: Ping-Ke Shih <pkshih@realtek.com> Tzu-En Huang <tehuang@realtek.com> Yan-Hsuan Chuang <yhchuang@realtek.com> Reviewed-by: Stanislaw Gruszka <sgruszka@redhat.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
90 lines
4.3 KiB
C
90 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_TX_H_
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#define __RTW_TX_H_
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#define RTK_TX_MAX_AGG_NUM_MASK 0x1f
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#define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500)
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#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
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#define SET_TX_DESC_OFFSET(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
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#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
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#define SET_TX_DESC_QSEL(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
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#define SET_TX_DESC_BMC(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
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#define SET_TX_DESC_RATE_ID(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16))
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#define SET_TX_DESC_DATARATE(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0))
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#define SET_TX_DESC_DISDATAFB(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10))
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#define SET_TX_DESC_USE_RATE(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8))
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#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22))
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#define SET_TX_DESC_DATA_BW(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5))
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#define SET_TX_DESC_SW_SEQ(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12))
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#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17))
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#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20))
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#define SET_TX_DESC_DATA_STBC(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8))
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#define SET_TX_DESC_DATA_LDPC(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7))
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#define SET_TX_DESC_AGG_EN(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12))
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#define SET_TX_DESC_LS(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26))
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#define SET_TX_DESC_DATA_SHORT(txdesc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4))
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#define SET_TX_DESC_SPE_RPT(tx_desc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19))
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#define SET_TX_DESC_SW_DEFINE(tx_desc, value) \
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le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0))
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enum rtw_tx_desc_queue_select {
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TX_DESC_QSEL_TID0 = 0,
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TX_DESC_QSEL_TID1 = 1,
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TX_DESC_QSEL_TID2 = 2,
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TX_DESC_QSEL_TID3 = 3,
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TX_DESC_QSEL_TID4 = 4,
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TX_DESC_QSEL_TID5 = 5,
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TX_DESC_QSEL_TID6 = 6,
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TX_DESC_QSEL_TID7 = 7,
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TX_DESC_QSEL_TID8 = 8,
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TX_DESC_QSEL_TID9 = 9,
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TX_DESC_QSEL_TID10 = 10,
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TX_DESC_QSEL_TID11 = 11,
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TX_DESC_QSEL_TID12 = 12,
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TX_DESC_QSEL_TID13 = 13,
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TX_DESC_QSEL_TID14 = 14,
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TX_DESC_QSEL_TID15 = 15,
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TX_DESC_QSEL_BEACON = 16,
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TX_DESC_QSEL_HIGH = 17,
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TX_DESC_QSEL_MGMT = 18,
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TX_DESC_QSEL_H2C = 19,
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};
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void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
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struct rtw_tx_pkt_info *pkt_info,
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struct ieee80211_tx_control *control,
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struct sk_buff *skb);
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void rtw_tx_fill_tx_desc(struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb);
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void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn);
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void rtw_tx_report_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
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void rtw_rsvd_page_pkt_info_update(struct rtw_dev *rtwdev,
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struct rtw_tx_pkt_info *pkt_info,
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struct sk_buff *skb);
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#endif
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