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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4c18e77f71
Multiple peripherals in SPEAr share common hardware interrupt lines. This patch adds support for a shared irq layer, which registers hardware irqs by itself and exposes virtual irq numbers to peripherals. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
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* arch/arm/plat-spear/shirq.c
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*
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* SPEAr platform shared irq layer source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <plat/shirq.h>
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struct spear_shirq *shirq;
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static DEFINE_SPINLOCK(lock);
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static void shirq_irq_mask(unsigned irq)
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{
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struct spear_shirq *shirq = get_irq_chip_data(irq);
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u32 val, id = irq - shirq->dev_config[0].virq;
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unsigned long flags;
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if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
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return;
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spin_lock_irqsave(&lock, flags);
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val = readl(shirq->regs.base + shirq->regs.enb_reg);
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if (shirq->regs.reset_to_enb)
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val |= shirq->dev_config[id].enb_mask;
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else
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val &= ~(shirq->dev_config[id].enb_mask);
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writel(val, shirq->regs.base + shirq->regs.enb_reg);
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spin_unlock_irqrestore(&lock, flags);
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}
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static void shirq_irq_unmask(unsigned irq)
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{
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struct spear_shirq *shirq = get_irq_chip_data(irq);
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u32 val, id = irq - shirq->dev_config[0].virq;
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unsigned long flags;
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if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
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return;
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spin_lock_irqsave(&lock, flags);
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val = readl(shirq->regs.base + shirq->regs.enb_reg);
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if (shirq->regs.reset_to_enb)
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val &= ~(shirq->dev_config[id].enb_mask);
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else
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val |= shirq->dev_config[id].enb_mask;
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writel(val, shirq->regs.base + shirq->regs.enb_reg);
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spin_unlock_irqrestore(&lock, flags);
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}
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static struct irq_chip shirq_chip = {
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.name = "spear_shirq",
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.ack = shirq_irq_mask,
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.mask = shirq_irq_mask,
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.unmask = shirq_irq_unmask,
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};
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static void shirq_handler(unsigned irq, struct irq_desc *desc)
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{
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u32 i, val, mask;
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struct spear_shirq *shirq = get_irq_data(irq);
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desc->chip->ack(irq);
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while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
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shirq->regs.status_reg_mask)) {
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for (i = 0; (i < shirq->dev_count) && val; i++) {
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if (!(shirq->dev_config[i].status_mask & val))
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continue;
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generic_handle_irq(shirq->dev_config[i].virq);
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/* clear interrupt */
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val &= ~shirq->dev_config[i].status_mask;
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if ((shirq->regs.clear_reg == -1) ||
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shirq->dev_config[i].clear_mask == -1)
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continue;
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mask = readl(shirq->regs.base + shirq->regs.clear_reg);
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if (shirq->regs.reset_to_clear)
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mask &= ~shirq->dev_config[i].clear_mask;
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else
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mask |= shirq->dev_config[i].clear_mask;
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writel(mask, shirq->regs.base + shirq->regs.clear_reg);
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}
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}
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desc->chip->unmask(irq);
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}
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int spear_shirq_register(struct spear_shirq *shirq)
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{
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int i;
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if (!shirq || !shirq->dev_config || !shirq->regs.base)
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return -EFAULT;
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if (!shirq->dev_count)
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return -EINVAL;
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set_irq_chained_handler(shirq->irq, shirq_handler);
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for (i = 0; i < shirq->dev_count; i++) {
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set_irq_chip(shirq->dev_config[i].virq, &shirq_chip);
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set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq);
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set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
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set_irq_chip_data(shirq->dev_config[i].virq, shirq);
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}
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set_irq_data(shirq->irq, shirq);
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return 0;
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}
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