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For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to "cdns,phy-type"-properties found in link subnodes under the managed serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree bindings for details). All other values of "cdns,phy-type"-property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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Kconfig | ||
Makefile | ||
phy-am654-serdes.c | ||
phy-da8xx-usb.c | ||
phy-dm816x-usb.c | ||
phy-gmii-sel.c | ||
phy-j721e-wiz.c | ||
phy-omap-control.c | ||
phy-omap-usb2.c | ||
phy-ti-pipe3.c | ||
phy-tusb1210.c | ||
phy-twl4030-usb.c |