mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 04:36:56 +07:00
dea1ffbeea
This patch adds support to tdm ports in AFE. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
212 lines
7.9 KiB
C
212 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __Q6AFE_H__
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#define __Q6AFE_H__
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#include <dt-bindings/sound/qcom,q6afe.h>
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#define AFE_PORT_MAX 105
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#define MSM_AFE_PORT_TYPE_RX 0
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#define MSM_AFE_PORT_TYPE_TX 1
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#define AFE_MAX_PORTS AFE_PORT_MAX
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#define Q6AFE_MAX_MI2S_LINES 4
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#define AFE_MAX_CHAN_COUNT 8
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#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
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#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
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#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
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#define LPAIF_DIG_CLK 1
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#define LPAIF_BIT_CLK 2
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#define LPAIF_OSR_CLK 3
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/* Clock ID for Primary I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
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/* Clock ID for Primary I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
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/* Clock ID for Secondary I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
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/* Clock ID for Secondary I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
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/* Clock ID for Tertiary I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
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/* Clock ID for Tertiary I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
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/* Clock ID for Quartnery I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
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/* Clock ID for Quartnery I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
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/* Clock ID for Speaker I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
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/* Clock ID for Speaker I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
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/* Clock ID for Speaker I2S OSR */
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#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
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/* Clock ID for QUINARY I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
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/* Clock ID for QUINARY I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
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/* Clock ID for SENARY I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
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/* Clock ID for SENARY I2S EBIT */
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#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
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/* Clock ID for INT0 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
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/* Clock ID for INT1 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
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/* Clock ID for INT2 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
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/* Clock ID for INT3 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
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/* Clock ID for INT4 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
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/* Clock ID for INT5 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
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/* Clock ID for INT6 I2S IBIT */
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#define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
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/* Clock ID for QUINARY MI2S OSR CLK */
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#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
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/* Clock ID for Primary PCM IBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
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/* Clock ID for Primary PCM EBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
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/* Clock ID for Secondary PCM IBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
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/* Clock ID for Secondary PCM EBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
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/* Clock ID for Tertiary PCM IBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
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/* Clock ID for Tertiary PCM EBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
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/* Clock ID for Quartery PCM IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
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/* Clock ID for Quartery PCM EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
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/* Clock ID for Quinary PCM IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
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/* Clock ID for Quinary PCM EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
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/* Clock ID for QUINARY PCM OSR */
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#define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
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/** Clock ID for Primary TDM IBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
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/** Clock ID for Primary TDM EBIT */
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#define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
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/** Clock ID for Secondary TDM IBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
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/** Clock ID for Secondary TDM EBIT */
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#define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
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/** Clock ID for Tertiary TDM IBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
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/** Clock ID for Tertiary TDM EBIT */
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#define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
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/** Clock ID for Quartery TDM IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
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/** Clock ID for Quartery TDM EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
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/** Clock ID for Quinary TDM IBIT */
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#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
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/** Clock ID for Quinary TDM EBIT */
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#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
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/** Clock ID for Quinary TDM OSR */
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#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
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/* Clock ID for MCLK1 */
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#define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
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/* Clock ID for MCLK2 */
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#define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
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/* Clock ID for MCLK3 */
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#define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
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/* Clock ID for MCLK4 */
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#define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
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/* Clock ID for Internal Digital Codec Core */
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#define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
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/* Clock ID for INT MCLK0 */
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#define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
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/* Clock ID for INT MCLK1 */
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#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
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/* Clock attribute for invalid use (reserved for internal usage) */
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#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
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/* Clock attribute for no couple case */
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#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
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/* Clock attribute for dividend couple case */
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#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
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/* Clock attribute for divisor couple case */
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#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
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/* Clock attribute for invert and no couple case */
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#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
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#define Q6AFE_CMAP_INVALID 0xFFFF
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struct q6afe_hdmi_cfg {
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u16 datatype;
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u16 channel_allocation;
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u32 sample_rate;
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u16 bit_width;
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};
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struct q6afe_slim_cfg {
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u32 sample_rate;
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u16 bit_width;
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u16 data_format;
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u16 num_channels;
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u8 ch_mapping[AFE_MAX_CHAN_COUNT];
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};
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struct q6afe_i2s_cfg {
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u32 sample_rate;
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u16 bit_width;
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u16 data_format;
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u16 num_channels;
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u32 sd_line_mask;
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int fmt;
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};
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struct q6afe_tdm_cfg {
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u16 num_channels;
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u32 sample_rate;
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u16 bit_width;
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u16 data_format;
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u16 sync_mode;
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u16 sync_src;
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u16 nslots_per_frame;
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u16 slot_width;
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u16 slot_mask;
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u32 data_align_type;
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u16 ch_mapping[AFE_MAX_CHAN_COUNT];
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};
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struct q6afe_port_config {
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struct q6afe_hdmi_cfg hdmi;
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struct q6afe_slim_cfg slim;
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struct q6afe_i2s_cfg i2s_cfg;
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struct q6afe_tdm_cfg tdm;
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};
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struct q6afe_port;
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struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
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int q6afe_port_start(struct q6afe_port *port);
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int q6afe_port_stop(struct q6afe_port *port);
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void q6afe_port_put(struct q6afe_port *port);
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int q6afe_get_port_id(int index);
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void q6afe_hdmi_port_prepare(struct q6afe_port *port,
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struct q6afe_hdmi_cfg *cfg);
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void q6afe_slim_port_prepare(struct q6afe_port *port,
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struct q6afe_slim_cfg *cfg);
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int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
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void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
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int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
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int clk_src, int clk_root,
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unsigned int freq, int dir);
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#endif /* __Q6AFE_H__ */
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