Cyrille Pitchen 51cca920ce ARM: dts: at91: sama5d2_xplained: Add QSPI0 + SPI NOR memory nodes ... This patch enables the QSPI0 controller, configures its pin muxing and declares a jedec,spi-nor memory. sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash memory which advertises a maximum frequency of 80MHz for Quad IO Fast Read. Set the spi-max-frequency to 80MHz knowing that actually the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com> Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200403061222.1277147-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>		2020-04-13 13:00:09 +02:00
..
bootp
compressed	SPDX patches for 5.7-rc1.	2020-04-03 13:12:26 -07:00
dts	ARM: dts: at91: sama5d2_xplained: Add QSPI0 + SPI NOR memory nodes	2020-04-13 13:00:09 +02:00
.gitignore	.gitignore: add SPDX License Identifier	2020-03-25 11:50:48 +01:00
deflate_xip_data.sh
install.sh
Makefile