mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 01:56:42 +07:00
3a638ff272
Add support for true pause and unpause. Without this, mplayer will drop some audio (less than one second, but still noticeable) when pausing playback. Remove support for PM suspend and resume from the trigger function, since the driver doesn't support PM anyway. Optimize the delay after starting capture. Instead of delaying 1ms, the driver now polls the hardware. The new delay is shorter by over 90% yet still effective. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
864 lines
27 KiB
C
864 lines
27 KiB
C
/*
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* Freescale DMA ALSA SoC PCM driver
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
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* under the terms of the GNU General Public License version 2. This
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* program is licensed "as is" without any warranty of any kind, whether
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* express or implied.
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*
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* This driver implements ASoC support for the Elo DMA controller, which is
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* the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
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* the PCM driver is what handles the DMA buffer.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <asm/io.h>
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#include "fsl_dma.h"
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/*
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* The formats that the DMA controller supports, which is anything
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* that is 8, 16, or 32 bits.
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*/
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#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_U8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S16_BE | \
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SNDRV_PCM_FMTBIT_U16_LE | \
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SNDRV_PCM_FMTBIT_U16_BE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S24_BE | \
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SNDRV_PCM_FMTBIT_U24_LE | \
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SNDRV_PCM_FMTBIT_U24_BE | \
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SNDRV_PCM_FMTBIT_S32_LE | \
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SNDRV_PCM_FMTBIT_S32_BE | \
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SNDRV_PCM_FMTBIT_U32_LE | \
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SNDRV_PCM_FMTBIT_U32_BE)
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#define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
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SNDRV_PCM_RATE_CONTINUOUS)
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/* DMA global data. This structure is used by fsl_dma_open() to determine
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* which DMA channels to assign to a substream. Unfortunately, ASoC V1 does
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* not allow the machine driver to provide this information to the PCM
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* driver in advance, and there's no way to differentiate between the two
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* DMA controllers. So for now, this driver only supports one SSI device
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* using two DMA channels. We cannot support multiple DMA devices.
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*
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* ssi_stx_phys: bus address of SSI STX register
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* ssi_srx_phys: bus address of SSI SRX register
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* dma_channel: pointer to the DMA channel's registers
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* irq: IRQ for this DMA channel
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* assigned: set to 1 if that DMA channel is assigned to a substream
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*/
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static struct {
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dma_addr_t ssi_stx_phys;
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dma_addr_t ssi_srx_phys;
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struct ccsr_dma_channel __iomem *dma_channel[2];
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unsigned int irq[2];
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unsigned int assigned[2];
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} dma_global_data;
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/*
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* The number of DMA links to use. Two is the bare minimum, but if you
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* have really small links you might need more.
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*/
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#define NUM_DMA_LINKS 2
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/** fsl_dma_private: p-substream DMA data
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*
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* Each substream has a 1-to-1 association with a DMA channel.
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*
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* The link[] array is first because it needs to be aligned on a 32-byte
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* boundary, so putting it first will ensure alignment without padding the
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* structure.
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*
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* @link[]: array of link descriptors
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* @controller_id: which DMA controller (0, 1, ...)
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* @channel_id: which DMA channel on the controller (0, 1, 2, ...)
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* @dma_channel: pointer to the DMA channel's registers
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* @irq: IRQ for this DMA channel
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* @substream: pointer to the substream object, needed by the ISR
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* @ssi_sxx_phys: bus address of the STX or SRX register to use
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* @ld_buf_phys: physical address of the LD buffer
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* @current_link: index into link[] of the link currently being processed
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* @dma_buf_phys: physical address of the DMA buffer
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* @dma_buf_next: physical address of the next period to process
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* @dma_buf_end: physical address of the byte after the end of the DMA
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* @buffer period_size: the size of a single period
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* @num_periods: the number of periods in the DMA buffer
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*/
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struct fsl_dma_private {
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struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
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unsigned int controller_id;
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unsigned int channel_id;
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struct ccsr_dma_channel __iomem *dma_channel;
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unsigned int irq;
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struct snd_pcm_substream *substream;
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dma_addr_t ssi_sxx_phys;
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dma_addr_t ld_buf_phys;
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unsigned int current_link;
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dma_addr_t dma_buf_phys;
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dma_addr_t dma_buf_next;
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dma_addr_t dma_buf_end;
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size_t period_size;
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unsigned int num_periods;
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};
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/**
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* fsl_dma_hardare: define characteristics of the PCM hardware.
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*
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* The PCM hardware is the Freescale DMA controller. This structure defines
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* the capabilities of that hardware.
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*
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* Since the sampling rate and data format are not controlled by the DMA
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* controller, we specify no limits for those values. The only exception is
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* period_bytes_min, which is set to a reasonably low value to prevent the
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* DMA controller from generating too many interrupts per second.
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*
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* Since each link descriptor has a 32-bit byte count field, we set
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* period_bytes_max to the largest 32-bit number. We also have no maximum
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* number of periods.
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*
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* Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
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* limitation in the SSI driver requires the sample rates for playback and
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* capture to be the same.
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*/
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static const struct snd_pcm_hardware fsl_dma_hardware = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_JOINT_DUPLEX |
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SNDRV_PCM_INFO_PAUSE,
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.formats = FSLDMA_PCM_FORMATS,
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.rates = FSLDMA_PCM_RATES,
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.rate_min = 5512,
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.rate_max = 192000,
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.period_bytes_min = 512, /* A reasonable limit */
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.period_bytes_max = (u32) -1,
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.periods_min = NUM_DMA_LINKS,
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.periods_max = (unsigned int) -1,
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.buffer_bytes_max = 128 * 1024, /* A reasonable limit */
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};
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/**
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* fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
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*
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* This function should be called by the ISR whenever the DMA controller
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* halts data transfer.
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*/
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static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
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{
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unsigned long flags;
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snd_pcm_stream_lock_irqsave(substream, flags);
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if (snd_pcm_running(substream))
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snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
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snd_pcm_stream_unlock_irqrestore(substream, flags);
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}
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/**
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* fsl_dma_update_pointers - update LD pointers to point to the next period
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*
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* As each period is completed, this function changes the the link
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* descriptor pointers for that period to point to the next period.
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*/
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static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
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{
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struct fsl_dma_link_descriptor *link =
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&dma_private->link[dma_private->current_link];
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/* Update our link descriptors to point to the next period */
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if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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link->source_addr =
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cpu_to_be32(dma_private->dma_buf_next);
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else
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link->dest_addr =
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cpu_to_be32(dma_private->dma_buf_next);
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/* Update our variables for next time */
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dma_private->dma_buf_next += dma_private->period_size;
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if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
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dma_private->dma_buf_next = dma_private->dma_buf_phys;
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if (++dma_private->current_link >= NUM_DMA_LINKS)
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dma_private->current_link = 0;
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}
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/**
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* fsl_dma_isr: interrupt handler for the DMA controller
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*
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* @irq: IRQ of the DMA channel
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* @dev_id: pointer to the dma_private structure for this DMA channel
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*/
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static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
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{
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struct fsl_dma_private *dma_private = dev_id;
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struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
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irqreturn_t ret = IRQ_NONE;
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u32 sr, sr2 = 0;
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/* We got an interrupt, so read the status register to see what we
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were interrupted for.
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*/
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sr = in_be32(&dma_channel->sr);
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if (sr & CCSR_DMA_SR_TE) {
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dev_err(dma_private->substream->pcm->card->dev,
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"DMA transmit error (controller=%u channel=%u irq=%u\n",
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dma_private->controller_id,
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dma_private->channel_id, irq);
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fsl_dma_abort_stream(dma_private->substream);
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sr2 |= CCSR_DMA_SR_TE;
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ret = IRQ_HANDLED;
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}
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if (sr & CCSR_DMA_SR_CH)
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ret = IRQ_HANDLED;
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if (sr & CCSR_DMA_SR_PE) {
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dev_err(dma_private->substream->pcm->card->dev,
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"DMA%u programming error (channel=%u irq=%u)\n",
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dma_private->controller_id,
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dma_private->channel_id, irq);
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fsl_dma_abort_stream(dma_private->substream);
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sr2 |= CCSR_DMA_SR_PE;
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ret = IRQ_HANDLED;
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}
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if (sr & CCSR_DMA_SR_EOLNI) {
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sr2 |= CCSR_DMA_SR_EOLNI;
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ret = IRQ_HANDLED;
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}
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if (sr & CCSR_DMA_SR_CB)
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ret = IRQ_HANDLED;
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if (sr & CCSR_DMA_SR_EOSI) {
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struct snd_pcm_substream *substream = dma_private->substream;
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/* Tell ALSA we completed a period. */
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snd_pcm_period_elapsed(substream);
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/*
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* Update our link descriptors to point to the next period. We
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* only need to do this if the number of periods is not equal to
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* the number of links.
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*/
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if (dma_private->num_periods != NUM_DMA_LINKS)
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fsl_dma_update_pointers(dma_private);
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sr2 |= CCSR_DMA_SR_EOSI;
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ret = IRQ_HANDLED;
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}
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if (sr & CCSR_DMA_SR_EOLSI) {
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sr2 |= CCSR_DMA_SR_EOLSI;
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ret = IRQ_HANDLED;
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}
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/* Clear the bits that we set */
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if (sr2)
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out_be32(&dma_channel->sr, sr2);
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return ret;
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}
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/**
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* fsl_dma_new: initialize this PCM driver.
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*
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* This function is called when the codec driver calls snd_soc_new_pcms(),
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* once for each .dai_link in the machine driver's snd_soc_card
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* structure.
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*/
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static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
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struct snd_pcm *pcm)
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{
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static u64 fsl_dma_dmamask = DMA_BIT_MASK(32);
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int ret;
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if (!card->dev->dma_mask)
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card->dev->dma_mask = &fsl_dma_dmamask;
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if (!card->dev->coherent_dma_mask)
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card->dev->coherent_dma_mask = fsl_dma_dmamask;
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
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fsl_dma_hardware.buffer_bytes_max,
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&pcm->streams[0].substream->dma_buffer);
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if (ret) {
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dev_err(card->dev,
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"Can't allocate playback DMA buffer (size=%u)\n",
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fsl_dma_hardware.buffer_bytes_max);
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return -ENOMEM;
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}
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev,
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fsl_dma_hardware.buffer_bytes_max,
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&pcm->streams[1].substream->dma_buffer);
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if (ret) {
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snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
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dev_err(card->dev,
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"Can't allocate capture DMA buffer (size=%u)\n",
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fsl_dma_hardware.buffer_bytes_max);
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return -ENOMEM;
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}
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return 0;
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}
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/**
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* fsl_dma_open: open a new substream.
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*
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* Each substream has its own DMA buffer.
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*
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* ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
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* descriptors that ping-pong from one period to the next. For example, if
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* there are six periods and two link descriptors, this is how they look
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* before playback starts:
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*
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* The last link descriptor
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* ____________ points back to the first
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* | |
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* V V
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* _________________________________________
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* | | | | | | | The DMA buffer is
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* | | | | | | | divided into 6 parts
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* |______|______|______|______|______|______|
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*
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* and here's how they look after the first period is finished playing:
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*
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* ____________
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* |______________
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* | |
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* V V
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* _________________________________________
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* | | | | | | |
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* | | | | | | |
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* |______|______|______|______|______|______|
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*
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* The first link descriptor now points to the third period. The DMA
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* controller is currently playing the second period. When it finishes, it
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* will jump back to the first descriptor and play the third period.
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*
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* There are four reasons we do this:
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*
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* 1. The only way to get the DMA controller to automatically restart the
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* transfer when it gets to the end of the buffer is to use chaining
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* mode. Basic direct mode doesn't offer that feature.
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* 2. We need to receive an interrupt at the end of every period. The DMA
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* controller can generate an interrupt at the end of every link transfer
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* (aka segment). Making each period into a DMA segment will give us the
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* interrupts we need.
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* 3. By creating only two link descriptors, regardless of the number of
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* periods, we do not need to reallocate the link descriptors if the
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* number of periods changes.
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* 4. All of the audio data is still stored in a single, contiguous DMA
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* buffer, which is what ALSA expects. We're just dividing it into
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* contiguous parts, and creating a link descriptor for each one.
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*/
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static int fsl_dma_open(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private;
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struct ccsr_dma_channel __iomem *dma_channel;
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dma_addr_t ld_buf_phys;
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u64 temp_link; /* Pointer to next link descriptor */
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u32 mr;
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unsigned int channel;
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int ret = 0;
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unsigned int i;
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/*
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* Reject any DMA buffer whose size is not a multiple of the period
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* size. We need to make sure that the DMA buffer can be evenly divided
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* into periods.
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*/
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ret = snd_pcm_hw_constraint_integer(runtime,
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SNDRV_PCM_HW_PARAM_PERIODS);
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if (ret < 0) {
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dev_err(substream->pcm->card->dev, "invalid buffer size\n");
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return ret;
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}
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channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
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if (dma_global_data.assigned[channel]) {
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dev_err(substream->pcm->card->dev,
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"DMA channel already assigned\n");
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return -EBUSY;
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}
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dma_private = dma_alloc_coherent(substream->pcm->dev,
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sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL);
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if (!dma_private) {
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dev_err(substream->pcm->card->dev,
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"can't allocate DMA private data\n");
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return -ENOMEM;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys;
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else
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dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys;
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dma_private->dma_channel = dma_global_data.dma_channel[channel];
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dma_private->irq = dma_global_data.irq[channel];
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dma_private->substream = substream;
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dma_private->ld_buf_phys = ld_buf_phys;
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dma_private->dma_buf_phys = substream->dma_buffer.addr;
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/* We only support one DMA controller for now */
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dma_private->controller_id = 0;
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dma_private->channel_id = channel;
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ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
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if (ret) {
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dev_err(substream->pcm->card->dev,
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"can't register ISR for IRQ %u (ret=%i)\n",
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dma_private->irq, ret);
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dma_free_coherent(substream->pcm->dev,
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sizeof(struct fsl_dma_private),
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dma_private, dma_private->ld_buf_phys);
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return ret;
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}
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dma_global_data.assigned[channel] = 1;
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snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
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snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
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runtime->private_data = dma_private;
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/* Program the fixed DMA controller parameters */
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dma_channel = dma_private->dma_channel;
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|
|
temp_link = dma_private->ld_buf_phys +
|
|
sizeof(struct fsl_dma_link_descriptor);
|
|
|
|
for (i = 0; i < NUM_DMA_LINKS; i++) {
|
|
dma_private->link[i].next = cpu_to_be64(temp_link);
|
|
|
|
temp_link += sizeof(struct fsl_dma_link_descriptor);
|
|
}
|
|
/* The last link descriptor points to the first */
|
|
dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
|
|
|
|
/* Tell the DMA controller where the first link descriptor is */
|
|
out_be32(&dma_channel->clndar,
|
|
CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
|
|
out_be32(&dma_channel->eclndar,
|
|
CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
|
|
|
|
/* The manual says the BCR must be clear before enabling EMP */
|
|
out_be32(&dma_channel->bcr, 0);
|
|
|
|
/*
|
|
* Program the mode register for interrupts, external master control,
|
|
* and source/destination hold. Also clear the Channel Abort bit.
|
|
*/
|
|
mr = in_be32(&dma_channel->mr) &
|
|
~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
|
|
|
|
/*
|
|
* We want External Master Start and External Master Pause enabled,
|
|
* because the SSI is controlling the DMA controller. We want the DMA
|
|
* controller to be set up in advance, and then we signal only the SSI
|
|
* to start transferring.
|
|
*
|
|
* We want End-Of-Segment Interrupts enabled, because this will generate
|
|
* an interrupt at the end of each segment (each link descriptor
|
|
* represents one segment). Each DMA segment is the same thing as an
|
|
* ALSA period, so this is how we get an interrupt at the end of every
|
|
* period.
|
|
*
|
|
* We want Error Interrupt enabled, so that we can get an error if
|
|
* the DMA controller is mis-programmed somehow.
|
|
*/
|
|
mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
|
|
CCSR_DMA_MR_EMS_EN;
|
|
|
|
/* For playback, we want the destination address to be held. For
|
|
capture, set the source address to be held. */
|
|
mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
|
|
CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
|
|
|
|
out_be32(&dma_channel->mr, mr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_hw_params: continue initializing the DMA links
|
|
*
|
|
* This function obtains hardware parameters about the opened stream and
|
|
* programs the DMA controller accordingly.
|
|
*
|
|
* One drawback of big-endian is that when copying integers of different
|
|
* sizes to a fixed-sized register, the address to which the integer must be
|
|
* copied is dependent on the size of the integer.
|
|
*
|
|
* For example, if P is the address of a 32-bit register, and X is a 32-bit
|
|
* integer, then X should be copied to address P. However, if X is a 16-bit
|
|
* integer, then it should be copied to P+2. If X is an 8-bit register,
|
|
* then it should be copied to P+3.
|
|
*
|
|
* So for playback of 8-bit samples, the DMA controller must transfer single
|
|
* bytes from the DMA buffer to the last byte of the STX0 register, i.e.
|
|
* offset by 3 bytes. For 16-bit samples, the offset is two bytes.
|
|
*
|
|
* For 24-bit samples, the offset is 1 byte. However, the DMA controller
|
|
* does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
|
|
* and 8 bytes at a time). So we do not support packed 24-bit samples.
|
|
* 24-bit data must be padded to 32 bits.
|
|
*/
|
|
static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *hw_params)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_dma_private *dma_private = runtime->private_data;
|
|
|
|
/* Number of bits per sample */
|
|
unsigned int sample_size =
|
|
snd_pcm_format_physical_width(params_format(hw_params));
|
|
|
|
/* Number of bytes per frame */
|
|
unsigned int frame_size = 2 * (sample_size / 8);
|
|
|
|
/* Bus address of SSI STX register */
|
|
dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
|
|
|
|
/* Size of the DMA buffer, in bytes */
|
|
size_t buffer_size = params_buffer_bytes(hw_params);
|
|
|
|
/* Number of bytes per period */
|
|
size_t period_size = params_period_bytes(hw_params);
|
|
|
|
/* Pointer to next period */
|
|
dma_addr_t temp_addr = substream->dma_buffer.addr;
|
|
|
|
/* Pointer to DMA controller */
|
|
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
|
|
|
|
u32 mr; /* DMA Mode Register */
|
|
|
|
unsigned int i;
|
|
|
|
/* Initialize our DMA tracking variables */
|
|
dma_private->period_size = period_size;
|
|
dma_private->num_periods = params_periods(hw_params);
|
|
dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
|
|
dma_private->dma_buf_next = dma_private->dma_buf_phys +
|
|
(NUM_DMA_LINKS * period_size);
|
|
|
|
if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
|
|
/* This happens if the number of periods == NUM_DMA_LINKS */
|
|
dma_private->dma_buf_next = dma_private->dma_buf_phys;
|
|
|
|
mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
|
|
CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
|
|
|
|
/* Due to a quirk of the SSI's STX register, the target address
|
|
* for the DMA operations depends on the sample size. So we calculate
|
|
* that offset here. While we're at it, also tell the DMA controller
|
|
* how much data to transfer per sample.
|
|
*/
|
|
switch (sample_size) {
|
|
case 8:
|
|
mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
|
|
ssi_sxx_phys += 3;
|
|
break;
|
|
case 16:
|
|
mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
|
|
ssi_sxx_phys += 2;
|
|
break;
|
|
case 32:
|
|
mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
|
|
break;
|
|
default:
|
|
/* We should never get here */
|
|
dev_err(substream->pcm->card->dev,
|
|
"unsupported sample size %u\n", sample_size);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* BWC should always be a multiple of the frame size. BWC determines
|
|
* how many bytes are sent/received before the DMA controller checks the
|
|
* SSI to see if it needs to stop. For playback, the transmit FIFO can
|
|
* hold three frames, so we want to send two frames at a time. For
|
|
* capture, the receive FIFO is triggered when it contains one frame, so
|
|
* we want to receive one frame at a time.
|
|
*/
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
mr |= CCSR_DMA_MR_BWC(2 * frame_size);
|
|
else
|
|
mr |= CCSR_DMA_MR_BWC(frame_size);
|
|
|
|
out_be32(&dma_channel->mr, mr);
|
|
|
|
for (i = 0; i < NUM_DMA_LINKS; i++) {
|
|
struct fsl_dma_link_descriptor *link = &dma_private->link[i];
|
|
|
|
link->count = cpu_to_be32(period_size);
|
|
|
|
/* Even though the DMA controller supports 36-bit addressing,
|
|
* for simplicity we allow only 32-bit addresses for the audio
|
|
* buffer itself. This was enforced in fsl_dma_new() with the
|
|
* DMA mask.
|
|
*
|
|
* The snoop bit tells the DMA controller whether it should tell
|
|
* the ECM to snoop during a read or write to an address. For
|
|
* audio, we use DMA to transfer data between memory and an I/O
|
|
* device (the SSI's STX0 or SRX0 register). Snooping is only
|
|
* needed if there is a cache, so we need to snoop memory
|
|
* addresses only. For playback, that means we snoop the source
|
|
* but not the destination. For capture, we snoop the
|
|
* destination but not the source.
|
|
*
|
|
* Note that failing to snoop properly is unlikely to cause
|
|
* cache incoherency if the period size is larger than the
|
|
* size of L1 cache. This is because filling in one period will
|
|
* flush out the data for the previous period. So if you
|
|
* increased period_bytes_min to a large enough size, you might
|
|
* get more performance by not snooping, and you'll still be
|
|
* okay.
|
|
*/
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
link->source_addr = cpu_to_be32(temp_addr);
|
|
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
|
|
|
|
link->dest_addr = cpu_to_be32(ssi_sxx_phys);
|
|
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
|
|
} else {
|
|
link->source_addr = cpu_to_be32(ssi_sxx_phys);
|
|
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
|
|
|
|
link->dest_addr = cpu_to_be32(temp_addr);
|
|
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
|
|
}
|
|
|
|
temp_addr += period_size;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_pointer: determine the current position of the DMA transfer
|
|
*
|
|
* This function is called by ALSA when ALSA wants to know where in the
|
|
* stream buffer the hardware currently is.
|
|
*
|
|
* For playback, the SAR register contains the physical address of the most
|
|
* recent DMA transfer. For capture, the value is in the DAR register.
|
|
*
|
|
* The base address of the buffer is stored in the source_addr field of the
|
|
* first link descriptor.
|
|
*/
|
|
static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_dma_private *dma_private = runtime->private_data;
|
|
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
|
|
dma_addr_t position;
|
|
snd_pcm_uframes_t frames;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
position = in_be32(&dma_channel->sar);
|
|
else
|
|
position = in_be32(&dma_channel->dar);
|
|
|
|
frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
|
|
|
|
/*
|
|
* If the current address is just past the end of the buffer, wrap it
|
|
* around.
|
|
*/
|
|
if (frames == runtime->buffer_size)
|
|
frames = 0;
|
|
|
|
return frames;
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
|
|
*
|
|
* Release the resources allocated in fsl_dma_hw_params() and de-program the
|
|
* registers.
|
|
*
|
|
* This function can be called multiple times.
|
|
*/
|
|
static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_dma_private *dma_private = runtime->private_data;
|
|
|
|
if (dma_private) {
|
|
struct ccsr_dma_channel __iomem *dma_channel;
|
|
|
|
dma_channel = dma_private->dma_channel;
|
|
|
|
/* Stop the DMA */
|
|
out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
|
|
out_be32(&dma_channel->mr, 0);
|
|
|
|
/* Reset all the other registers */
|
|
out_be32(&dma_channel->sr, -1);
|
|
out_be32(&dma_channel->clndar, 0);
|
|
out_be32(&dma_channel->eclndar, 0);
|
|
out_be32(&dma_channel->satr, 0);
|
|
out_be32(&dma_channel->sar, 0);
|
|
out_be32(&dma_channel->datr, 0);
|
|
out_be32(&dma_channel->dar, 0);
|
|
out_be32(&dma_channel->bcr, 0);
|
|
out_be32(&dma_channel->nlndar, 0);
|
|
out_be32(&dma_channel->enlndar, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* fsl_dma_close: close the stream.
|
|
*/
|
|
static int fsl_dma_close(struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
struct fsl_dma_private *dma_private = runtime->private_data;
|
|
int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
|
|
|
|
if (dma_private) {
|
|
if (dma_private->irq)
|
|
free_irq(dma_private->irq, dma_private);
|
|
|
|
if (dma_private->ld_buf_phys) {
|
|
dma_unmap_single(substream->pcm->dev,
|
|
dma_private->ld_buf_phys,
|
|
sizeof(dma_private->link), DMA_TO_DEVICE);
|
|
}
|
|
|
|
/* Deallocate the fsl_dma_private structure */
|
|
dma_free_coherent(substream->pcm->dev,
|
|
sizeof(struct fsl_dma_private),
|
|
dma_private, dma_private->ld_buf_phys);
|
|
substream->runtime->private_data = NULL;
|
|
}
|
|
|
|
dma_global_data.assigned[dir] = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Remove this PCM driver.
|
|
*/
|
|
static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
|
|
{
|
|
struct snd_pcm_substream *substream;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
|
|
substream = pcm->streams[i].substream;
|
|
if (substream) {
|
|
snd_dma_free_pages(&substream->dma_buffer);
|
|
substream->dma_buffer.area = NULL;
|
|
substream->dma_buffer.addr = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
static struct snd_pcm_ops fsl_dma_ops = {
|
|
.open = fsl_dma_open,
|
|
.close = fsl_dma_close,
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
.hw_params = fsl_dma_hw_params,
|
|
.hw_free = fsl_dma_hw_free,
|
|
.pointer = fsl_dma_pointer,
|
|
};
|
|
|
|
struct snd_soc_platform fsl_soc_platform = {
|
|
.name = "fsl-dma",
|
|
.pcm_ops = &fsl_dma_ops,
|
|
.pcm_new = fsl_dma_new,
|
|
.pcm_free = fsl_dma_free_dma_buffers,
|
|
};
|
|
EXPORT_SYMBOL_GPL(fsl_soc_platform);
|
|
|
|
/**
|
|
* fsl_dma_configure: store the DMA parameters from the fabric driver.
|
|
*
|
|
* This function is called by the ASoC fabric driver to give us the DMA and
|
|
* SSI channel information.
|
|
*
|
|
* Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI
|
|
* data when a substream is created, so for now we need to store this data
|
|
* into a global variable. This means that we can only support one DMA
|
|
* controller, and hence only one SSI.
|
|
*/
|
|
int fsl_dma_configure(struct fsl_dma_info *dma_info)
|
|
{
|
|
static int initialized;
|
|
|
|
/* We only support one DMA controller for now */
|
|
if (initialized)
|
|
return 0;
|
|
|
|
dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys;
|
|
dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys;
|
|
dma_global_data.dma_channel[0] = dma_info->dma_channel[0];
|
|
dma_global_data.dma_channel[1] = dma_info->dma_channel[1];
|
|
dma_global_data.irq[0] = dma_info->dma_irq[0];
|
|
dma_global_data.irq[1] = dma_info->dma_irq[1];
|
|
dma_global_data.assigned[0] = 0;
|
|
dma_global_data.assigned[1] = 0;
|
|
|
|
initialized = 1;
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fsl_dma_configure);
|
|
|
|
static int __init fsl_soc_platform_init(void)
|
|
{
|
|
return snd_soc_register_platform(&fsl_soc_platform);
|
|
}
|
|
module_init(fsl_soc_platform_init);
|
|
|
|
static void __exit fsl_soc_platform_exit(void)
|
|
{
|
|
snd_soc_unregister_platform(&fsl_soc_platform);
|
|
}
|
|
module_exit(fsl_soc_platform_exit);
|
|
|
|
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
|
|
MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module");
|
|
MODULE_LICENSE("GPL");
|