mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 14:55:04 +07:00
ce6e118846
This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
|
|
* Purna Chandra Mandal,<purna.mandal@microchip.com>
|
|
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
|
|
*
|
|
* This program is free software; you can distribute it and/or modify it
|
|
* under the terms of the GNU General Public License (Version 2) as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
* for more details.
|
|
*/
|
|
#ifndef __MICROCHIP_CLK_PIC32_H_
|
|
#define __MICROCHIP_CLK_PIC32_H_
|
|
|
|
#include <linux/clk-provider.h>
|
|
|
|
/* PIC32 clock data */
|
|
struct pic32_clk_common {
|
|
struct device *dev;
|
|
void __iomem *iobase;
|
|
spinlock_t reg_lock; /* clock lock */
|
|
};
|
|
|
|
/* System PLL clock */
|
|
struct pic32_sys_pll_data {
|
|
struct clk_init_data init_data;
|
|
const u32 ctrl_reg;
|
|
const u32 status_reg;
|
|
const u32 lock_mask;
|
|
};
|
|
|
|
/* System clock */
|
|
struct pic32_sys_clk_data {
|
|
struct clk_init_data init_data;
|
|
const u32 mux_reg;
|
|
const u32 slew_reg;
|
|
const u32 *parent_map;
|
|
const u32 slew_div;
|
|
};
|
|
|
|
/* Reference Oscillator clock */
|
|
struct pic32_ref_osc_data {
|
|
struct clk_init_data init_data;
|
|
const u32 ctrl_reg;
|
|
const u32 *parent_map;
|
|
};
|
|
|
|
/* Peripheral Bus clock */
|
|
struct pic32_periph_clk_data {
|
|
struct clk_init_data init_data;
|
|
const u32 ctrl_reg;
|
|
};
|
|
|
|
/* External Secondary Oscillator clock */
|
|
struct pic32_sec_osc_data {
|
|
struct clk_init_data init_data;
|
|
const u32 enable_reg;
|
|
const u32 status_reg;
|
|
const u32 enable_mask;
|
|
const u32 status_mask;
|
|
const unsigned long fixed_rate;
|
|
};
|
|
|
|
extern const struct clk_ops pic32_pbclk_ops;
|
|
extern const struct clk_ops pic32_sclk_ops;
|
|
extern const struct clk_ops pic32_sclk_no_div_ops;
|
|
extern const struct clk_ops pic32_spll_ops;
|
|
extern const struct clk_ops pic32_roclk_ops;
|
|
extern const struct clk_ops pic32_sosc_ops;
|
|
|
|
struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data,
|
|
struct pic32_clk_common *core);
|
|
struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
|
|
struct pic32_clk_common *core);
|
|
struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
|
|
struct pic32_clk_common *core);
|
|
struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
|
|
struct pic32_clk_common *core);
|
|
struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data,
|
|
struct pic32_clk_common *core);
|
|
|
|
#endif /* __MICROCHIP_CLK_PIC32_H_*/
|