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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9be1c8afb4
Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
107 lines
3.5 KiB
C
107 lines
3.5 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
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#define _DT_BINDINGS_RST_SUN8I_H3_H_
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#define RST_USB_PHY0 0
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#define RST_USB_PHY1 1
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#define RST_USB_PHY2 2
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#define RST_USB_PHY3 3
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#define RST_MBUS 4
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#define RST_BUS_CE 5
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#define RST_BUS_DMA 6
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#define RST_BUS_MMC0 7
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#define RST_BUS_MMC1 8
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#define RST_BUS_MMC2 9
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#define RST_BUS_NAND 10
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#define RST_BUS_DRAM 11
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#define RST_BUS_EMAC 12
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#define RST_BUS_TS 13
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#define RST_BUS_HSTIMER 14
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#define RST_BUS_SPI0 15
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#define RST_BUS_SPI1 16
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#define RST_BUS_OTG 17
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#define RST_BUS_EHCI0 18
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#define RST_BUS_EHCI1 19
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#define RST_BUS_EHCI2 20
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#define RST_BUS_EHCI3 21
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#define RST_BUS_OHCI0 22
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#define RST_BUS_OHCI1 23
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#define RST_BUS_OHCI2 24
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#define RST_BUS_OHCI3 25
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#define RST_BUS_VE 26
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#define RST_BUS_TCON0 27
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#define RST_BUS_TCON1 28
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#define RST_BUS_DEINTERLACE 29
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#define RST_BUS_CSI 30
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#define RST_BUS_TVE 31
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#define RST_BUS_HDMI0 32
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#define RST_BUS_HDMI1 33
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#define RST_BUS_DE 34
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#define RST_BUS_GPU 35
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#define RST_BUS_MSGBOX 36
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#define RST_BUS_SPINLOCK 37
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#define RST_BUS_DBG 38
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#define RST_BUS_EPHY 39
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#define RST_BUS_CODEC 40
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#define RST_BUS_SPDIF 41
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#define RST_BUS_THS 42
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#define RST_BUS_I2S0 43
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#define RST_BUS_I2S1 44
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#define RST_BUS_I2S2 45
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#define RST_BUS_I2C0 46
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#define RST_BUS_I2C1 47
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#define RST_BUS_I2C2 48
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#define RST_BUS_UART0 49
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#define RST_BUS_UART1 50
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#define RST_BUS_UART2 51
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#define RST_BUS_UART3 52
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#define RST_BUS_SCR0 53
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/* New resets imported in H5 */
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#define RST_BUS_SCR1 54
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#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
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