Thierry Reding 51511d05de drm/tegra: sor: Write correct head state registers ... The head state registers are per head, so they must be properly indexed. This has worked fine so far because all boards with eDP use it as the primary output, so it is very likely to end up attached to head 0. Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-08-13 13:47:56 +02:00
..
drm	drm/tegra: sor: Write correct head state registers	2015-08-13 13:47:56 +02:00
host1x	gpu: host1x: mipi: Power down regulators when unused	2015-08-13 13:47:21 +02:00
ipu-v3	GPU: ipu: Fix race in installing IPU chained IRQ handler	2015-06-18 14:03:08 +02:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00