mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:03:28 +07:00
514743357f
Drop use of drmp.h from all header files in drm/gma500. Fix fallout in all files. In some cases moved include lines and sorted them too. With drmP.h removed from all header files it can now be removed from each .c file without any further dependencies Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190519195526.3422-3-sam@ravnborg.org
378 lines
12 KiB
C
378 lines
12 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* jim liu <jim.liu@intel.com>
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* Jackie Li<yaodong.li@intel.com>
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*/
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#ifndef __MDFLD_DSI_OUTPUT_H__
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#define __MDFLD_DSI_OUTPUT_H__
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#include <linux/backlight.h>
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#include <drm/drm.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "mdfld_output.h"
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#include <asm/intel-mid.h>
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
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#define FLD_MOD(orig, val, start, end) \
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(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
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#define REG_FLD_MOD(reg, val, start, end) \
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REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
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static inline int REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg,
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u32 val, int start, int end)
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{
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int t = 100000;
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while (FLD_GET(REG_READ(reg), start, end) != val) {
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if (--t == 0)
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return 1;
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}
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return 0;
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}
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#define REG_FLD_WAIT(reg, val, start, end) \
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REGISTER_FLD_WAIT(dev, reg, val, start, end)
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#define REG_BIT_WAIT(reg, val, bitnum) \
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REGISTER_FLD_WAIT(dev, reg, val, bitnum, bitnum)
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#define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100
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#ifdef DEBUG
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#define CHECK_PIPE(pipe) ({ \
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const typeof(pipe) __pipe = (pipe); \
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BUG_ON(__pipe != 0 && __pipe != 2); \
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__pipe; })
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#else
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#define CHECK_PIPE(pipe) (pipe)
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#endif
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/*
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* Actual MIPIA->MIPIC reg offset is 0x800, value 0x400 is valid for 0 and 2
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*/
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#define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400)
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/* mdfld DSI controller registers */
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#define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe))
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#define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe))
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#define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe))
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#define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe))
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#define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe))
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#define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe))
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#define MIPI_TURN_AROUND_TIMEOUT_REG(pipe) (0xb018 + REG_OFFSET(pipe))
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#define MIPI_DEVICE_RESET_TIMER_REG(pipe) (0xb01c + REG_OFFSET(pipe))
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#define MIPI_DPI_RESOLUTION_REG(pipe) (0xb020 + REG_OFFSET(pipe))
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#define MIPI_DBI_FIFO_THROTTLE_REG(pipe) (0xb024 + REG_OFFSET(pipe))
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#define MIPI_HSYNC_COUNT_REG(pipe) (0xb028 + REG_OFFSET(pipe))
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#define MIPI_HBP_COUNT_REG(pipe) (0xb02c + REG_OFFSET(pipe))
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#define MIPI_HFP_COUNT_REG(pipe) (0xb030 + REG_OFFSET(pipe))
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#define MIPI_HACTIVE_COUNT_REG(pipe) (0xb034 + REG_OFFSET(pipe))
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#define MIPI_VSYNC_COUNT_REG(pipe) (0xb038 + REG_OFFSET(pipe))
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#define MIPI_VBP_COUNT_REG(pipe) (0xb03c + REG_OFFSET(pipe))
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#define MIPI_VFP_COUNT_REG(pipe) (0xb040 + REG_OFFSET(pipe))
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#define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe) (0xb044 + REG_OFFSET(pipe))
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#define MIPI_DPI_CONTROL_REG(pipe) (0xb048 + REG_OFFSET(pipe))
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#define MIPI_DPI_DATA_REG(pipe) (0xb04c + REG_OFFSET(pipe))
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#define MIPI_INIT_COUNT_REG(pipe) (0xb050 + REG_OFFSET(pipe))
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#define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe) (0xb054 + REG_OFFSET(pipe))
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#define MIPI_VIDEO_MODE_FORMAT_REG(pipe) (0xb058 + REG_OFFSET(pipe))
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#define MIPI_EOT_DISABLE_REG(pipe) (0xb05c + REG_OFFSET(pipe))
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#define MIPI_LP_BYTECLK_REG(pipe) (0xb060 + REG_OFFSET(pipe))
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#define MIPI_LP_GEN_DATA_REG(pipe) (0xb064 + REG_OFFSET(pipe))
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#define MIPI_HS_GEN_DATA_REG(pipe) (0xb068 + REG_OFFSET(pipe))
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#define MIPI_LP_GEN_CTRL_REG(pipe) (0xb06c + REG_OFFSET(pipe))
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#define MIPI_HS_GEN_CTRL_REG(pipe) (0xb070 + REG_OFFSET(pipe))
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#define MIPI_GEN_FIFO_STAT_REG(pipe) (0xb074 + REG_OFFSET(pipe))
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#define MIPI_HS_LS_DBI_ENABLE_REG(pipe) (0xb078 + REG_OFFSET(pipe))
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#define MIPI_DPHY_PARAM_REG(pipe) (0xb080 + REG_OFFSET(pipe))
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#define MIPI_DBI_BW_CTRL_REG(pipe) (0xb084 + REG_OFFSET(pipe))
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#define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe) (0xb088 + REG_OFFSET(pipe))
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#define MIPI_CTRL_REG(pipe) (0xb104 + REG_OFFSET(pipe))
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#define MIPI_DATA_ADD_REG(pipe) (0xb108 + REG_OFFSET(pipe))
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#define MIPI_DATA_LEN_REG(pipe) (0xb10c + REG_OFFSET(pipe))
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#define MIPI_CMD_ADD_REG(pipe) (0xb110 + REG_OFFSET(pipe))
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#define MIPI_CMD_LEN_REG(pipe) (0xb114 + REG_OFFSET(pipe))
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/* non-uniform reg offset */
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#define MIPI_PORT_CONTROL(pipe) (CHECK_PIPE(pipe) ? MIPI_C : MIPI)
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#define DSI_DEVICE_READY (0x1)
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#define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
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#define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
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#define DSI_POWER_STATE_ULPS_OFFSET (0x1)
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#define DSI_ONE_DATA_LANE (0x1)
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#define DSI_TWO_DATA_LANE (0x2)
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#define DSI_THREE_DATA_LANE (0X3)
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#define DSI_FOUR_DATA_LANE (0x4)
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#define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
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#define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
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#define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
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#define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
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#define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
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#define DSI_INTR_STATE_RXSOTERROR BIT(0)
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#define DSI_INTR_STATE_SPL_PKG_SENT BIT(30)
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#define DSI_INTR_STATE_TE BIT(31)
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#define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
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#define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
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#define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
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#define DSI_RESET_TIMER_MASK (0xffff)
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#define DSI_DBI_FIFO_WM_HALF (0x0)
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#define DSI_DBI_FIFO_WM_QUARTER (0x1)
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#define DSI_DBI_FIFO_WM_LOW (0x2)
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#define DSI_DPI_TIMING_MASK (0xffff)
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#define DSI_INIT_TIMER_MASK (0xffff)
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#define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
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#define DSI_LP_BYTECLK_MASK (0x0ffff)
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#define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
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#define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
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#define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
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#define DSI_HS_CTRL_GEN_R0 (0x04)
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#define DSI_HS_CTRL_GEN_R1 (0x14)
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#define DSI_HS_CTRL_GEN_R2 (0x24)
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#define DSI_HS_CTRL_GEN_LONG_W (0x29)
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#define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
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#define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
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#define DSI_HS_CTRL_MCS_R0 (0x06)
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#define DSI_HS_CTRL_MCS_LONG_W (0x39)
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#define DSI_HS_CTRL_VC_OFFSET (0x06)
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#define DSI_HS_CTRL_WC_OFFSET (0x08)
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#define DSI_FIFO_GEN_HS_DATA_FULL BIT(0)
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#define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY BIT(1)
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#define DSI_FIFO_GEN_HS_DATA_EMPTY BIT(2)
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#define DSI_FIFO_GEN_LP_DATA_FULL BIT(8)
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#define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY BIT(9)
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#define DSI_FIFO_GEN_LP_DATA_EMPTY BIT(10)
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#define DSI_FIFO_GEN_HS_CTRL_FULL BIT(16)
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#define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY BIT(17)
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#define DSI_FIFO_GEN_HS_CTRL_EMPTY BIT(18)
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#define DSI_FIFO_GEN_LP_CTRL_FULL BIT(24)
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#define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY BIT(25)
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#define DSI_FIFO_GEN_LP_CTRL_EMPTY BIT(26)
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#define DSI_FIFO_DBI_EMPTY BIT(27)
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#define DSI_FIFO_DPI_EMPTY BIT(28)
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#define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
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#define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
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#define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
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#define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
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#define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
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/*dsi power modes*/
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#define DSI_POWER_MODE_DISPLAY_ON BIT(2)
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#define DSI_POWER_MODE_NORMAL_ON BIT(3)
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#define DSI_POWER_MODE_SLEEP_OUT BIT(4)
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#define DSI_POWER_MODE_PARTIAL_ON BIT(5)
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#define DSI_POWER_MODE_IDLE_ON BIT(6)
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enum {
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MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
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MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
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MDFLD_DSI_VIDEO_BURST_MODE = 3,
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};
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#define DSI_DPI_COMPLETE_LAST_LINE BIT(2)
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#define DSI_DPI_DISABLE_BTA BIT(3)
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struct mdfld_dsi_connector {
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struct gma_connector base;
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int pipe;
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void *private;
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void *pkg_sender;
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/* Connection status */
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enum drm_connector_status status;
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};
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struct mdfld_dsi_encoder {
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struct gma_encoder base;
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void *private;
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};
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/*
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* DSI config, consists of one DSI connector, two DSI encoders.
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* DRM will pick up on DSI encoder basing on differents configs.
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*/
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struct mdfld_dsi_config {
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struct drm_device *dev;
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struct drm_display_mode *fixed_mode;
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struct drm_display_mode *mode;
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struct mdfld_dsi_connector *connector;
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struct mdfld_dsi_encoder *encoder;
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int changed;
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int bpp;
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int lane_count;
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/*Virtual channel number for this encoder*/
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int channel_num;
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/*video mode configure*/
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int video_mode;
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int dvr_ic_inited;
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};
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static inline struct mdfld_dsi_connector *mdfld_dsi_connector(
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struct drm_connector *connector)
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{
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struct gma_connector *gma_connector;
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gma_connector = to_gma_connector(connector);
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return container_of(gma_connector, struct mdfld_dsi_connector, base);
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}
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static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder(
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struct drm_encoder *encoder)
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{
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struct gma_encoder *gma_encoder;
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gma_encoder = to_gma_encoder(encoder);
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return container_of(gma_encoder, struct mdfld_dsi_encoder, base);
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}
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static inline struct mdfld_dsi_config *
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mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
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{
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if (!connector)
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return NULL;
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return (struct mdfld_dsi_config *)connector->private;
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}
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static inline void *mdfld_dsi_get_pkg_sender(struct mdfld_dsi_config *config)
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{
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struct mdfld_dsi_connector *dsi_connector;
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if (!config)
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return NULL;
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dsi_connector = config->connector;
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if (!dsi_connector)
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return NULL;
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return dsi_connector->pkg_sender;
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}
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static inline struct mdfld_dsi_config *
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mdfld_dsi_encoder_get_config(struct mdfld_dsi_encoder *encoder)
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{
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if (!encoder)
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return NULL;
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return (struct mdfld_dsi_config *)encoder->private;
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}
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static inline struct mdfld_dsi_connector *
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mdfld_dsi_encoder_get_connector(struct mdfld_dsi_encoder *encoder)
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{
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struct mdfld_dsi_config *config;
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if (!encoder)
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return NULL;
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config = mdfld_dsi_encoder_get_config(encoder);
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if (!config)
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return NULL;
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return config->connector;
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}
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static inline void *mdfld_dsi_encoder_get_pkg_sender(
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struct mdfld_dsi_encoder *encoder)
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{
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struct mdfld_dsi_config *dsi_config;
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dsi_config = mdfld_dsi_encoder_get_config(encoder);
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if (!dsi_config)
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return NULL;
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return mdfld_dsi_get_pkg_sender(dsi_config);
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}
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static inline int mdfld_dsi_encoder_get_pipe(struct mdfld_dsi_encoder *encoder)
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{
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struct mdfld_dsi_connector *connector;
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if (!encoder)
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return -1;
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connector = mdfld_dsi_encoder_get_connector(encoder);
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if (!connector)
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return -1;
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return connector->pipe;
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}
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/* Export functions */
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extern void mdfld_dsi_gen_fifo_ready(struct drm_device *dev,
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u32 gen_fifo_stat_reg, u32 fifo_stat);
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extern void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config,
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int pipe);
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extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
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int level);
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extern void mdfld_dsi_output_init(struct drm_device *dev,
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int pipe,
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const struct panel_funcs *p_vid_funcs);
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extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
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int pipe);
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extern int mdfld_dsi_get_power_mode(struct mdfld_dsi_config *dsi_config,
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u32 *mode, bool hs);
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extern int mdfld_dsi_panel_reset(int pipe);
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#endif /*__MDFLD_DSI_OUTPUT_H__*/
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