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df5d6ecf81
Support for TLB reservation (or TLB Write Conditional) and Paired MAS registers are optional for a processor implementation so we handle them via MMU feature sections. We currently only used paired MAS registers to access the full RPN + perm bits that are kept in MAS7||MAS3. We assume that if an implementation has hardware page table at this time it also implements in TLB reservations. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
771 lines
23 KiB
ArmAsm
771 lines
23 KiB
ArmAsm
/*
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* Low leve TLB miss handlers for Book3E
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*
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* Copyright (C) 2008-2009
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* Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/pgtable.h>
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#include <asm/reg.h>
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#include <asm/exception-64e.h>
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#include <asm/ppc-opcode.h>
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#ifdef CONFIG_PPC_64K_PAGES
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#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
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#else
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#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
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#endif
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#define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
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#define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
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#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
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/**********************************************************************
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* *
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* TLB miss handling for Book3E with TLB reservation and HES support *
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* *
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**********************************************************************/
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/* Data TLB miss */
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START_EXCEPTION(data_tlb_miss)
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TLB_MISS_PROLOG
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/* Now we handle the fault proper. We only save DEAR in normal
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* fault case since that's the only interesting values here.
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* We could probably also optimize by not saving SRR0/1 in the
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* linear mapping case but I'll leave that for later
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*/
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mfspr r14,SPRN_ESR
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mfspr r16,SPRN_DEAR /* get faulting address */
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srdi r15,r16,60 /* get region */
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cmpldi cr0,r15,0xc /* linear mapping ? */
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TLB_MISS_STATS_SAVE_INFO
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beq tlb_load_linear /* yes -> go to linear map load */
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/* The page tables are mapped virtually linear. At this point, though,
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* we don't know whether we are trying to fault in a first level
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* virtual address or a virtual page table address. We can get that
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* from bit 0x1 of the region ID which we have set for a page table
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*/
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andi. r10,r15,0x1
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bne- virt_page_table_tlb_miss
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std r14,EX_TLB_ESR(r12); /* save ESR */
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std r16,EX_TLB_DEAR(r12); /* save DEAR */
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/* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
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li r11,_PAGE_PRESENT
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oris r11,r11,_PAGE_ACCESSED@h
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/* We do the user/kernel test for the PID here along with the RW test
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*/
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cmpldi cr0,r15,0 /* Check for user region */
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/* We pre-test some combination of permissions to avoid double
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* faults:
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*
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* We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
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* ESR_ST is 0x00800000
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* _PAGE_BAP_SW is 0x00000010
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* So the shift is >> 19. This tests for supervisor writeability.
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* If the page happens to be supervisor writeable and not user
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* writeable, we will take a new fault later, but that should be
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* a rare enough case.
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*
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* We also move ESR_ST in _PAGE_DIRTY position
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* _PAGE_DIRTY is 0x00001000 so the shift is >> 11
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*
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* MAS1 is preset for all we need except for TID that needs to
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* be cleared for kernel translations
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*/
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rlwimi r11,r14,32-19,27,27
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rlwimi r11,r14,32-16,19,19
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beq normal_tlb_miss
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/* XXX replace the RMW cycles with immediate loads + writes */
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1: mfspr r10,SPRN_MAS1
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cmpldi cr0,r15,8 /* Check for vmalloc region */
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rlwinm r10,r10,0,16,1 /* Clear TID */
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mtspr SPRN_MAS1,r10
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beq+ normal_tlb_miss
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/* We got a crappy address, just fault with whatever DEAR and ESR
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* are here
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*/
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TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
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TLB_MISS_EPILOG_ERROR
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b exc_data_storage_book3e
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/* Instruction TLB miss */
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START_EXCEPTION(instruction_tlb_miss)
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TLB_MISS_PROLOG
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/* If we take a recursive fault, the second level handler may need
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* to know whether we are handling a data or instruction fault in
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* order to get to the right store fault handler. We provide that
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* info by writing a crazy value in ESR in our exception frame
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*/
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li r14,-1 /* store to exception frame is done later */
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/* Now we handle the fault proper. We only save DEAR in the non
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* linear mapping case since we know the linear mapping case will
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* not re-enter. We could indeed optimize and also not save SRR0/1
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* in the linear mapping case but I'll leave that for later
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*
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* Faulting address is SRR0 which is already in r16
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*/
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srdi r15,r16,60 /* get region */
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cmpldi cr0,r15,0xc /* linear mapping ? */
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TLB_MISS_STATS_SAVE_INFO
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beq tlb_load_linear /* yes -> go to linear map load */
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/* We do the user/kernel test for the PID here along with the RW test
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*/
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li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
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oris r11,r11,_PAGE_ACCESSED@h
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cmpldi cr0,r15,0 /* Check for user region */
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std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
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beq normal_tlb_miss
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/* XXX replace the RMW cycles with immediate loads + writes */
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1: mfspr r10,SPRN_MAS1
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cmpldi cr0,r15,8 /* Check for vmalloc region */
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rlwinm r10,r10,0,16,1 /* Clear TID */
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mtspr SPRN_MAS1,r10
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beq+ normal_tlb_miss
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/* We got a crappy address, just fault */
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TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
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TLB_MISS_EPILOG_ERROR
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b exc_instruction_storage_book3e
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/*
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* This is the guts of the first-level TLB miss handler for direct
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* misses. We are entered with:
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*
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* r16 = faulting address
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* r15 = region ID
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* r14 = crap (free to use)
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* r13 = PACA
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* r12 = TLB exception frame in PACA
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* r11 = PTE permission mask
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* r10 = crap (free to use)
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*/
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normal_tlb_miss:
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/* So we first construct the page table address. We do that by
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* shifting the bottom of the address (not the region ID) by
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* PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
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* or'ing the fourth high bit.
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*
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* NOTE: For 64K pages, we do things slightly differently in
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* order to handle the weird page table format used by linux
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*/
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ori r10,r15,0x1
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#ifdef CONFIG_PPC_64K_PAGES
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/* For the top bits, 16 bytes per PTE */
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rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
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/* Now create the bottom bits as 0 in position 0x8000 and
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* the rest calculated for 8 bytes per PTE
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*/
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rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
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/* Insert the bottom bits in */
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rlwimi r14,r15,0,16,31
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#else
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rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
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#endif
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sldi r15,r10,60
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clrrdi r14,r14,3
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or r10,r15,r14
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BEGIN_MMU_FTR_SECTION
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/* Set the TLB reservation and seach for existing entry. Then load
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* the entry.
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*/
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PPC_TLBSRX_DOT(0,r16)
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ld r14,0(r10)
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beq normal_tlb_miss_done
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MMU_FTR_SECTION_ELSE
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ld r14,0(r10)
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
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finish_normal_tlb_miss:
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/* Check if required permissions are met */
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andc. r15,r11,r14
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bne- normal_tlb_miss_access_fault
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/* Now we build the MAS:
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*
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* MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
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* MAS 1 : Almost fully setup
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* - PID already updated by caller if necessary
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* - TSIZE need change if !base page size, not
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* yet implemented for now
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* MAS 2 : Defaults not useful, need to be redone
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* MAS 3+7 : Needs to be done
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*
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* TODO: mix up code below for better scheduling
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*/
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clrrdi r11,r16,12 /* Clear low crap in EA */
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rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
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mtspr SPRN_MAS2,r11
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/* Check page size, if not standard, update MAS1 */
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rldicl r11,r14,64-8,64-8
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#ifdef CONFIG_PPC_64K_PAGES
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cmpldi cr0,r11,BOOK3E_PAGESZ_64K
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#else
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cmpldi cr0,r11,BOOK3E_PAGESZ_4K
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#endif
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beq- 1f
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mfspr r11,SPRN_MAS1
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rlwimi r11,r14,31,21,24
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rlwinm r11,r11,0,21,19
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mtspr SPRN_MAS1,r11
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1:
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/* Move RPN in position */
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rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
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clrldi r15,r11,12 /* Clear crap at the top */
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rlwimi r15,r14,32-8,22,25 /* Move in U bits */
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rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
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/* Mask out SW and UW if !DIRTY (XXX optimize this !) */
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andi. r11,r14,_PAGE_DIRTY
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bne 1f
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li r11,MAS3_SW|MAS3_UW
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andc r15,r15,r11
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1:
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BEGIN_MMU_FTR_SECTION
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srdi r16,r15,32
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mtspr SPRN_MAS3,r15
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mtspr SPRN_MAS7,r16
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MMU_FTR_SECTION_ELSE
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mtspr SPRN_MAS7_MAS3,r15
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
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tlbwe
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normal_tlb_miss_done:
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/* We don't bother with restoring DEAR or ESR since we know we are
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* level 0 and just going back to userland. They are only needed
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* if you are going to take an access fault
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*/
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TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
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TLB_MISS_EPILOG_SUCCESS
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rfi
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normal_tlb_miss_access_fault:
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/* We need to check if it was an instruction miss */
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andi. r10,r11,_PAGE_EXEC
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bne 1f
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ld r14,EX_TLB_DEAR(r12)
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ld r15,EX_TLB_ESR(r12)
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mtspr SPRN_DEAR,r14
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mtspr SPRN_ESR,r15
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TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
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TLB_MISS_EPILOG_ERROR
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b exc_data_storage_book3e
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1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
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TLB_MISS_EPILOG_ERROR
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b exc_instruction_storage_book3e
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/*
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* This is the guts of the second-level TLB miss handler for direct
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* misses. We are entered with:
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*
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* r16 = virtual page table faulting address
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* r15 = region (top 4 bits of address)
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* r14 = crap (free to use)
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* r13 = PACA
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* r12 = TLB exception frame in PACA
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* r11 = crap (free to use)
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* r10 = crap (free to use)
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*
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* Note that this should only ever be called as a second level handler
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* with the current scheme when using SW load.
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* That means we can always get the original fault DEAR at
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* EX_TLB_DEAR-EX_TLB_SIZE(r12)
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*
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* It can be re-entered by the linear mapping miss handler. However, to
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* avoid too much complication, it will restart the whole fault at level
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* 0 so we don't care too much about clobbers
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*
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* XXX That code was written back when we couldn't clobber r14. We can now,
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* so we could probably optimize things a bit
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*/
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virt_page_table_tlb_miss:
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/* Are we hitting a kernel page table ? */
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andi. r10,r15,0x8
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/* The cool thing now is that r10 contains 0 for user and 8 for kernel,
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* and we happen to have the swapper_pg_dir at offset 8 from the user
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* pgdir in the PACA :-).
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*/
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add r11,r10,r13
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/* If kernel, we need to clear MAS1 TID */
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beq 1f
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/* XXX replace the RMW cycles with immediate loads + writes */
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mfspr r10,SPRN_MAS1
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rlwinm r10,r10,0,16,1 /* Clear TID */
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mtspr SPRN_MAS1,r10
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1:
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BEGIN_MMU_FTR_SECTION
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/* Search if we already have a TLB entry for that virtual address, and
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* if we do, bail out.
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*/
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PPC_TLBSRX_DOT(0,r16)
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beq virt_page_table_tlb_miss_done
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
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/* Now, we need to walk the page tables. First check if we are in
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* range.
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*/
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rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
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bne- virt_page_table_tlb_miss_fault
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/* Get the PGD pointer */
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ld r15,PACAPGD(r11)
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cmpldi cr0,r15,0
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beq- virt_page_table_tlb_miss_fault
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/* Get to PGD entry */
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rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
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clrrdi r10,r11,3
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ldx r15,r10,r15
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cmpldi cr0,r15,0
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beq virt_page_table_tlb_miss_fault
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#ifndef CONFIG_PPC_64K_PAGES
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/* Get to PUD entry */
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rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
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clrrdi r10,r11,3
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ldx r15,r10,r15
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cmpldi cr0,r15,0
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beq virt_page_table_tlb_miss_fault
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#endif /* CONFIG_PPC_64K_PAGES */
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/* Get to PMD entry */
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rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
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clrrdi r10,r11,3
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ldx r15,r10,r15
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cmpldi cr0,r15,0
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beq virt_page_table_tlb_miss_fault
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/* Ok, we're all right, we can now create a kernel translation for
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* a 4K or 64K page from r16 -> r15.
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*/
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/* Now we build the MAS:
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*
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* MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
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* MAS 1 : Almost fully setup
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* - PID already updated by caller if necessary
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* - TSIZE for now is base page size always
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* MAS 2 : Use defaults
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* MAS 3+7 : Needs to be done
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*
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* So we only do MAS 2 and 3 for now...
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*/
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clrldi r11,r15,4 /* remove region ID from RPN */
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ori r10,r11,1 /* Or-in SR */
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BEGIN_MMU_FTR_SECTION
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srdi r16,r10,32
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mtspr SPRN_MAS3,r10
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mtspr SPRN_MAS7,r16
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MMU_FTR_SECTION_ELSE
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mtspr SPRN_MAS7_MAS3,r10
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
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tlbwe
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BEGIN_MMU_FTR_SECTION
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virt_page_table_tlb_miss_done:
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/* We have overriden MAS2:EPN but currently our primary TLB miss
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* handler will always restore it so that should not be an issue,
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* if we ever optimize the primary handler to not write MAS2 on
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* some cases, we'll have to restore MAS2:EPN here based on the
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* original fault's DEAR. If we do that we have to modify the
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* ITLB miss handler to also store SRR0 in the exception frame
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* as DEAR.
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*
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* However, one nasty thing we did is we cleared the reservation
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* (well, potentially we did). We do a trick here thus if we
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* are not a level 0 exception (we interrupted the TLB miss) we
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* offset the return address by -4 in order to replay the tlbsrx
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* instruction there
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*/
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subf r10,r13,r12
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cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
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bne- 1f
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ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
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addi r10,r11,-4
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std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
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1:
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
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/* Return to caller, normal case */
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TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
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TLB_MISS_EPILOG_SUCCESS
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rfi
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virt_page_table_tlb_miss_fault:
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/* If we fault here, things are a little bit tricky. We need to call
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* either data or instruction store fault, and we need to retreive
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* the original fault address and ESR (for data).
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*
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* The thing is, we know that in normal circumstances, this is
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* always called as a second level tlb miss for SW load or as a first
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* level TLB miss for HW load, so we should be able to peek at the
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* relevant informations in the first exception frame in the PACA.
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*
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* However, we do need to double check that, because we may just hit
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* a stray kernel pointer or a userland attack trying to hit those
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* areas. If that is the case, we do a data fault. (We can't get here
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* from an instruction tlb miss anyway).
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*
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* Note also that when going to a fault, we must unwind the previous
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|
* level as well. Since we are doing that, we don't need to clear or
|
|
* restore the TLB reservation neither.
|
|
*/
|
|
subf r10,r13,r12
|
|
cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
|
|
bne- virt_page_table_tlb_miss_whacko_fault
|
|
|
|
/* We dig the original DEAR and ESR from slot 0 */
|
|
ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
|
|
ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
|
|
|
|
/* We check for the "special" ESR value for instruction faults */
|
|
cmpdi cr0,r16,-1
|
|
beq 1f
|
|
mtspr SPRN_DEAR,r15
|
|
mtspr SPRN_ESR,r16
|
|
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_data_storage_book3e
|
|
1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_instruction_storage_book3e
|
|
|
|
virt_page_table_tlb_miss_whacko_fault:
|
|
/* The linear fault will restart everything so ESR and DEAR will
|
|
* not have been clobbered, let's just fault with what we have
|
|
*/
|
|
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_data_storage_book3e
|
|
|
|
|
|
/**************************************************************
|
|
* *
|
|
* TLB miss handling for Book3E with hw page table support *
|
|
* *
|
|
**************************************************************/
|
|
|
|
|
|
/* Data TLB miss */
|
|
START_EXCEPTION(data_tlb_miss_htw)
|
|
TLB_MISS_PROLOG
|
|
|
|
/* Now we handle the fault proper. We only save DEAR in normal
|
|
* fault case since that's the only interesting values here.
|
|
* We could probably also optimize by not saving SRR0/1 in the
|
|
* linear mapping case but I'll leave that for later
|
|
*/
|
|
mfspr r14,SPRN_ESR
|
|
mfspr r16,SPRN_DEAR /* get faulting address */
|
|
srdi r11,r16,60 /* get region */
|
|
cmpldi cr0,r11,0xc /* linear mapping ? */
|
|
TLB_MISS_STATS_SAVE_INFO
|
|
beq tlb_load_linear /* yes -> go to linear map load */
|
|
|
|
/* We do the user/kernel test for the PID here along with the RW test
|
|
*/
|
|
cmpldi cr0,r11,0 /* Check for user region */
|
|
ld r15,PACAPGD(r13) /* Load user pgdir */
|
|
beq htw_tlb_miss
|
|
|
|
/* XXX replace the RMW cycles with immediate loads + writes */
|
|
1: mfspr r10,SPRN_MAS1
|
|
cmpldi cr0,r11,8 /* Check for vmalloc region */
|
|
rlwinm r10,r10,0,16,1 /* Clear TID */
|
|
mtspr SPRN_MAS1,r10
|
|
ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
|
|
beq+ htw_tlb_miss
|
|
|
|
/* We got a crappy address, just fault with whatever DEAR and ESR
|
|
* are here
|
|
*/
|
|
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_data_storage_book3e
|
|
|
|
/* Instruction TLB miss */
|
|
START_EXCEPTION(instruction_tlb_miss_htw)
|
|
TLB_MISS_PROLOG
|
|
|
|
/* If we take a recursive fault, the second level handler may need
|
|
* to know whether we are handling a data or instruction fault in
|
|
* order to get to the right store fault handler. We provide that
|
|
* info by keeping a crazy value for ESR in r14
|
|
*/
|
|
li r14,-1 /* store to exception frame is done later */
|
|
|
|
/* Now we handle the fault proper. We only save DEAR in the non
|
|
* linear mapping case since we know the linear mapping case will
|
|
* not re-enter. We could indeed optimize and also not save SRR0/1
|
|
* in the linear mapping case but I'll leave that for later
|
|
*
|
|
* Faulting address is SRR0 which is already in r16
|
|
*/
|
|
srdi r11,r16,60 /* get region */
|
|
cmpldi cr0,r11,0xc /* linear mapping ? */
|
|
TLB_MISS_STATS_SAVE_INFO
|
|
beq tlb_load_linear /* yes -> go to linear map load */
|
|
|
|
/* We do the user/kernel test for the PID here along with the RW test
|
|
*/
|
|
cmpldi cr0,r11,0 /* Check for user region */
|
|
ld r15,PACAPGD(r13) /* Load user pgdir */
|
|
beq htw_tlb_miss
|
|
|
|
/* XXX replace the RMW cycles with immediate loads + writes */
|
|
1: mfspr r10,SPRN_MAS1
|
|
cmpldi cr0,r11,8 /* Check for vmalloc region */
|
|
rlwinm r10,r10,0,16,1 /* Clear TID */
|
|
mtspr SPRN_MAS1,r10
|
|
ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
|
|
beq+ htw_tlb_miss
|
|
|
|
/* We got a crappy address, just fault */
|
|
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_instruction_storage_book3e
|
|
|
|
|
|
/*
|
|
* This is the guts of the second-level TLB miss handler for direct
|
|
* misses. We are entered with:
|
|
*
|
|
* r16 = virtual page table faulting address
|
|
* r15 = PGD pointer
|
|
* r14 = ESR
|
|
* r13 = PACA
|
|
* r12 = TLB exception frame in PACA
|
|
* r11 = crap (free to use)
|
|
* r10 = crap (free to use)
|
|
*
|
|
* It can be re-entered by the linear mapping miss handler. However, to
|
|
* avoid too much complication, it will save/restore things for us
|
|
*/
|
|
htw_tlb_miss:
|
|
/* Search if we already have a TLB entry for that virtual address, and
|
|
* if we do, bail out.
|
|
*
|
|
* MAS1:IND should be already set based on MAS4
|
|
*/
|
|
PPC_TLBSRX_DOT(0,r16)
|
|
beq htw_tlb_miss_done
|
|
|
|
/* Now, we need to walk the page tables. First check if we are in
|
|
* range.
|
|
*/
|
|
rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
|
|
bne- htw_tlb_miss_fault
|
|
|
|
/* Get the PGD pointer */
|
|
cmpldi cr0,r15,0
|
|
beq- htw_tlb_miss_fault
|
|
|
|
/* Get to PGD entry */
|
|
rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
|
|
clrrdi r10,r11,3
|
|
ldx r15,r10,r15
|
|
cmpldi cr0,r15,0
|
|
beq htw_tlb_miss_fault
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
/* Get to PUD entry */
|
|
rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
|
|
clrrdi r10,r11,3
|
|
ldx r15,r10,r15
|
|
cmpldi cr0,r15,0
|
|
beq htw_tlb_miss_fault
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
/* Get to PMD entry */
|
|
rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
|
|
clrrdi r10,r11,3
|
|
ldx r15,r10,r15
|
|
cmpldi cr0,r15,0
|
|
beq htw_tlb_miss_fault
|
|
|
|
/* Ok, we're all right, we can now create an indirect entry for
|
|
* a 1M or 256M page.
|
|
*
|
|
* The last trick is now that because we use "half" pages for
|
|
* the HTW (1M IND is 2K and 256M IND is 32K) we need to account
|
|
* for an added LSB bit to the RPN. For 64K pages, there is no
|
|
* problem as we already use 32K arrays (half PTE pages), but for
|
|
* 4K page we need to extract a bit from the virtual address and
|
|
* insert it into the "PA52" bit of the RPN.
|
|
*/
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
rlwimi r15,r16,32-9,20,20
|
|
#endif
|
|
/* Now we build the MAS:
|
|
*
|
|
* MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
|
|
* MAS 1 : Almost fully setup
|
|
* - PID already updated by caller if necessary
|
|
* - TSIZE for now is base ind page size always
|
|
* MAS 2 : Use defaults
|
|
* MAS 3+7 : Needs to be done
|
|
*/
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
|
|
#else
|
|
ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
|
|
#endif
|
|
|
|
BEGIN_MMU_FTR_SECTION
|
|
srdi r16,r10,32
|
|
mtspr SPRN_MAS3,r10
|
|
mtspr SPRN_MAS7,r16
|
|
MMU_FTR_SECTION_ELSE
|
|
mtspr SPRN_MAS7_MAS3,r10
|
|
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
|
|
|
|
tlbwe
|
|
|
|
htw_tlb_miss_done:
|
|
/* We don't bother with restoring DEAR or ESR since we know we are
|
|
* level 0 and just going back to userland. They are only needed
|
|
* if you are going to take an access fault
|
|
*/
|
|
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
|
|
TLB_MISS_EPILOG_SUCCESS
|
|
rfi
|
|
|
|
htw_tlb_miss_fault:
|
|
/* We need to check if it was an instruction miss. We know this
|
|
* though because r14 would contain -1
|
|
*/
|
|
cmpdi cr0,r14,-1
|
|
beq 1f
|
|
mtspr SPRN_DEAR,r16
|
|
mtspr SPRN_ESR,r14
|
|
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_data_storage_book3e
|
|
1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
|
|
TLB_MISS_EPILOG_ERROR
|
|
b exc_instruction_storage_book3e
|
|
|
|
/*
|
|
* This is the guts of "any" level TLB miss handler for kernel linear
|
|
* mapping misses. We are entered with:
|
|
*
|
|
*
|
|
* r16 = faulting address
|
|
* r15 = crap (free to use)
|
|
* r14 = ESR (data) or -1 (instruction)
|
|
* r13 = PACA
|
|
* r12 = TLB exception frame in PACA
|
|
* r11 = crap (free to use)
|
|
* r10 = crap (free to use)
|
|
*
|
|
* In addition we know that we will not re-enter, so in theory, we could
|
|
* use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
|
|
*
|
|
* We also need to be careful about MAS registers here & TLB reservation,
|
|
* as we know we'll have clobbered them if we interrupt the main TLB miss
|
|
* handlers in which case we probably want to do a full restart at level
|
|
* 0 rather than saving / restoring the MAS.
|
|
*
|
|
* Note: If we care about performance of that core, we can easily shuffle
|
|
* a few things around
|
|
*/
|
|
tlb_load_linear:
|
|
/* For now, we assume the linear mapping is contiguous and stops at
|
|
* linear_map_top. We also assume the size is a multiple of 1G, thus
|
|
* we only use 1G pages for now. That might have to be changed in a
|
|
* final implementation, especially when dealing with hypervisors
|
|
*/
|
|
ld r11,PACATOC(r13)
|
|
ld r11,linear_map_top@got(r11)
|
|
ld r10,0(r11)
|
|
cmpld cr0,r10,r16
|
|
bge tlb_load_linear_fault
|
|
|
|
/* MAS1 need whole new setup. */
|
|
li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
|
|
oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
|
|
mtspr SPRN_MAS1,r15
|
|
|
|
/* Already somebody there ? */
|
|
PPC_TLBSRX_DOT(0,r16)
|
|
beq tlb_load_linear_done
|
|
|
|
/* Now we build the remaining MAS. MAS0 and 2 should be fine
|
|
* with their defaults, which leaves us with MAS 3 and 7. The
|
|
* mapping is linear, so we just take the address, clear the
|
|
* region bits, and or in the permission bits which are currently
|
|
* hard wired
|
|
*/
|
|
clrrdi r10,r16,30 /* 1G page index */
|
|
clrldi r10,r10,4 /* clear region bits */
|
|
ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
|
|
|
|
BEGIN_MMU_FTR_SECTION
|
|
srdi r16,r10,32
|
|
mtspr SPRN_MAS3,r10
|
|
mtspr SPRN_MAS7,r16
|
|
MMU_FTR_SECTION_ELSE
|
|
mtspr SPRN_MAS7_MAS3,r10
|
|
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
|
|
|
|
tlbwe
|
|
|
|
tlb_load_linear_done:
|
|
/* We use the "error" epilog for success as we do want to
|
|
* restore to the initial faulting context, whatever it was.
|
|
* We do that because we can't resume a fault within a TLB
|
|
* miss handler, due to MAS and TLB reservation being clobbered.
|
|
*/
|
|
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
|
|
TLB_MISS_EPILOG_ERROR
|
|
rfi
|
|
|
|
tlb_load_linear_fault:
|
|
/* We keep the DEAR and ESR around, this shouldn't have happened */
|
|
cmpdi cr0,r14,-1
|
|
beq 1f
|
|
TLB_MISS_EPILOG_ERROR_SPECIAL
|
|
b exc_data_storage_book3e
|
|
1: TLB_MISS_EPILOG_ERROR_SPECIAL
|
|
b exc_instruction_storage_book3e
|
|
|
|
|
|
#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
|
|
.tlb_stat_inc:
|
|
1: ldarx r8,0,r9
|
|
addi r8,r8,1
|
|
stdcx. r8,0,r9
|
|
bne- 1b
|
|
blr
|
|
#endif
|