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The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies 32bit. Y210: For each component, valid data occupies MSB 10 bits. LSB 6 bits are filled with zeroes. Y212: For each component, valid data occupies MSB 12 bits. LSB 4 bits are filled with zeroes. Y216: For each component valid data occupies 16 bits, doesn't require any padding bits. First 16 bits stores the Y value and the next 16 bits stores one of the chroma samples alternatively. The first luma sample will be accompanied by first U sample and second luma sample is accompanied by the first V sample. The following pixel formats are packed format that follows 4:4:4 chroma sampling. Channels are arranged in the order UYVA in increasing memory order. Y410: Each color component occupies 10 bits and X component takes 2 bits, thus each pixel occupies 32 bits. Y412: Each color component is 16 bits where valid data occupies MSB 12 bits. LSB 4 bits are filled with zeroes. Thus, each pixel occupies 64 bits. Y416: Each color component occupies 16 bits for valid data, doesn't require any padding bits. Thus, each pixel occupies 64 bits. v3: fixed missing tab for XYUV8888 (JP) Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1551700595-21481-5-git-send-email-swati2.sharma@intel.com |
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amdgpu_drm.h | ||
armada_drm.h | ||
drm_fourcc.h | ||
drm_mode.h | ||
drm_sarea.h | ||
drm.h | ||
etnaviv_drm.h | ||
exynos_drm.h | ||
i810_drm.h | ||
i915_drm.h | ||
mga_drm.h | ||
msm_drm.h | ||
nouveau_drm.h | ||
omap_drm.h | ||
qxl_drm.h | ||
r128_drm.h | ||
radeon_drm.h | ||
savage_drm.h | ||
sis_drm.h | ||
tegra_drm.h | ||
v3d_drm.h | ||
vc4_drm.h | ||
vgem_drm.h | ||
via_drm.h | ||
virtgpu_drm.h | ||
vmwgfx_drm.h |