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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f7018c2135
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
306 lines
10 KiB
C
306 lines
10 KiB
C
/* drivers/video/msm_fb/mddi_hw.h
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*
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* MSM MDDI Hardware Registers and Structures
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*
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* Copyright (C) 2007 QUALCOMM Incorporated
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* Copyright (C) 2007 Google Incorporated
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MDDI_HW_H_
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#define _MDDI_HW_H_
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#include <linux/types.h>
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#define MDDI_CMD 0x0000
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#define MDDI_VERSION 0x0004
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#define MDDI_PRI_PTR 0x0008
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#define MDDI_SEC_PTR 0x000c
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#define MDDI_BPS 0x0010
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#define MDDI_SPM 0x0014
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#define MDDI_INT 0x0018
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#define MDDI_INTEN 0x001c
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#define MDDI_REV_PTR 0x0020
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#define MDDI_REV_SIZE 0x0024
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#define MDDI_STAT 0x0028
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#define MDDI_REV_RATE_DIV 0x002c
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#define MDDI_REV_CRC_ERR 0x0030
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#define MDDI_TA1_LEN 0x0034
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#define MDDI_TA2_LEN 0x0038
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#define MDDI_TEST_BUS 0x003c
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#define MDDI_TEST 0x0040
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#define MDDI_REV_PKT_CNT 0x0044
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#define MDDI_DRIVE_HI 0x0048
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#define MDDI_DRIVE_LO 0x004c
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#define MDDI_DISP_WAKE 0x0050
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#define MDDI_REV_ENCAP_SZ 0x0054
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#define MDDI_RTD_VAL 0x0058
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#define MDDI_PAD_CTL 0x0068
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#define MDDI_DRIVER_START_CNT 0x006c
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#define MDDI_NEXT_PRI_PTR 0x0070
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#define MDDI_NEXT_SEC_PTR 0x0074
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#define MDDI_MISR_CTL 0x0078
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#define MDDI_MISR_DATA 0x007c
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#define MDDI_SF_CNT 0x0080
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#define MDDI_MF_CNT 0x0084
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#define MDDI_CURR_REV_PTR 0x0088
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#define MDDI_CORE_VER 0x008c
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#define MDDI_INT_PRI_PTR_READ 0x0001
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#define MDDI_INT_SEC_PTR_READ 0x0002
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#define MDDI_INT_REV_DATA_AVAIL 0x0004
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#define MDDI_INT_DISP_REQ 0x0008
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#define MDDI_INT_PRI_UNDERFLOW 0x0010
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#define MDDI_INT_SEC_UNDERFLOW 0x0020
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#define MDDI_INT_REV_OVERFLOW 0x0040
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#define MDDI_INT_CRC_ERROR 0x0080
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#define MDDI_INT_MDDI_IN 0x0100
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#define MDDI_INT_PRI_OVERWRITE 0x0200
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#define MDDI_INT_SEC_OVERWRITE 0x0400
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#define MDDI_INT_REV_OVERWRITE 0x0800
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#define MDDI_INT_DMA_FAILURE 0x1000
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#define MDDI_INT_LINK_ACTIVE 0x2000
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#define MDDI_INT_IN_HIBERNATION 0x4000
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#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
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#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
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#define MDDI_INT_NO_CMD_PKTS_PEND 0x20000
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#define MDDI_INT_RTD_FAILURE 0x40000
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#define MDDI_INT_REV_PKT_RECEIVED 0x80000
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#define MDDI_INT_REV_PKTS_AVAIL 0x100000
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#define MDDI_INT_NEED_CLEAR ( \
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MDDI_INT_REV_DATA_AVAIL | \
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MDDI_INT_PRI_UNDERFLOW | \
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MDDI_INT_SEC_UNDERFLOW | \
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MDDI_INT_REV_OVERFLOW | \
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MDDI_INT_CRC_ERROR | \
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MDDI_INT_REV_PKT_RECEIVED)
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#define MDDI_STAT_LINK_ACTIVE 0x0001
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#define MDDI_STAT_NEW_REV_PTR 0x0002
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#define MDDI_STAT_NEW_PRI_PTR 0x0004
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#define MDDI_STAT_NEW_SEC_PTR 0x0008
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#define MDDI_STAT_IN_HIBERNATION 0x0010
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#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
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#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
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#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
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#define MDDI_STAT_PENDING_REV_ENCAP 0x0100
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#define MDDI_STAT_PENDING_POWERDOWN 0x0200
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#define MDDI_STAT_RTD_MEAS_FAIL 0x0800
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#define MDDI_STAT_CLIENT_WAKEUP_REQ 0x1000
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#define MDDI_CMD_POWERDOWN 0x0100
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#define MDDI_CMD_POWERUP 0x0200
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#define MDDI_CMD_HIBERNATE 0x0300
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#define MDDI_CMD_RESET 0x0400
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#define MDDI_CMD_DISP_IGNORE 0x0501
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#define MDDI_CMD_DISP_LISTEN 0x0500
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#define MDDI_CMD_SEND_REV_ENCAP 0x0600
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#define MDDI_CMD_GET_CLIENT_CAP 0x0601
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#define MDDI_CMD_GET_CLIENT_STATUS 0x0602
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#define MDDI_CMD_SEND_RTD 0x0700
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#define MDDI_CMD_LINK_ACTIVE 0x0900
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#define MDDI_CMD_PERIODIC_REV_ENCAP 0x0A00
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#define MDDI_CMD_FORCE_NEW_REV_PTR 0x0C00
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#define MDDI_VIDEO_REV_PKT_SIZE 0x40
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#define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE 0x60
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#define MDDI_MAX_REV_PKT_SIZE 0x60
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/* #define MDDI_REV_BUFFER_SIZE 128 */
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#define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
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/* MDP sends 256 pixel packets, so lower value hibernates more without
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* significantly increasing latency of waiting for next subframe */
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#define MDDI_HOST_BYTES_PER_SUBFRAME 0x3C00
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#define MDDI_HOST_TA2_LEN 0x000c
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#define MDDI_HOST_REV_RATE_DIV 0x0002
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struct __attribute__((packed)) mddi_rev_packet {
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uint16_t length;
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uint16_t type;
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uint16_t client_id;
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};
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struct __attribute__((packed)) mddi_client_status {
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uint16_t length;
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uint16_t type;
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uint16_t client_id;
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uint16_t reverse_link_request; /* bytes needed in rev encap message */
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uint8_t crc_error_count;
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uint8_t capability_change;
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uint16_t graphics_busy_flags;
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uint16_t crc16;
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};
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struct __attribute__((packed)) mddi_client_caps {
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uint16_t length; /* length, exclusive of this field */
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uint16_t type; /* 66 */
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uint16_t client_id;
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uint16_t Protocol_Version;
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uint16_t Minimum_Protocol_Version;
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uint16_t Data_Rate_Capability;
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uint8_t Interface_Type_Capability;
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uint8_t Number_of_Alt_Displays;
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uint16_t PostCal_Data_Rate;
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uint16_t Bitmap_Width;
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uint16_t Bitmap_Height;
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uint16_t Display_Window_Width;
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uint16_t Display_Window_Height;
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uint32_t Color_Map_Size;
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uint16_t Color_Map_RGB_Width;
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uint16_t RGB_Capability;
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uint8_t Monochrome_Capability;
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uint8_t Reserved_1;
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uint16_t Y_Cb_Cr_Capability;
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uint16_t Bayer_Capability;
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uint16_t Alpha_Cursor_Image_Planes;
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uint32_t Client_Feature_Capability_Indicators;
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uint8_t Maximum_Video_Frame_Rate_Capability;
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uint8_t Minimum_Video_Frame_Rate_Capability;
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uint16_t Minimum_Sub_frame_Rate;
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uint16_t Audio_Buffer_Depth;
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uint16_t Audio_Channel_Capability;
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uint16_t Audio_Sample_Rate_Capability;
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uint8_t Audio_Sample_Resolution;
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uint8_t Mic_Audio_Sample_Resolution;
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uint16_t Mic_Sample_Rate_Capability;
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uint8_t Keyboard_Data_Format;
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uint8_t pointing_device_data_format;
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uint16_t content_protection_type;
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uint16_t Mfr_Name;
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uint16_t Product_Code;
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uint16_t Reserved_3;
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uint32_t Serial_Number;
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uint8_t Week_of_Manufacture;
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uint8_t Year_of_Manufacture;
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uint16_t crc16;
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} mddi_client_capability_type;
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struct __attribute__((packed)) mddi_video_stream {
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uint16_t length;
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uint16_t type; /* 16 */
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uint16_t client_id; /* 0 */
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uint16_t video_data_format_descriptor;
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/* format of each pixel in the Pixel Data in the present stream in the
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* present packet.
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* If bits [15:13] = 000 monochrome
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* If bits [15:13] = 001 color pixels (palette).
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* If bits [15:13] = 010 color pixels in raw RGB
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* If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
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* If bits [15:13] = 100 Bayer pixels
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*/
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uint16_t pixel_data_attributes;
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/* interpreted as follows:
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* Bits [1:0] = 11 pixel data is displayed to both eyes
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* Bits [1:0] = 10 pixel data is routed to the left eye only.
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* Bits [1:0] = 01 pixel data is routed to the right eye only.
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* Bits [1:0] = 00 pixel data is routed to the alternate display.
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* Bit 2 is 0 Pixel Data is in the standard progressive format.
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* Bit 2 is 1 Pixel Data is in interlace format.
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* Bit 3 is 0 Pixel Data is in the standard progressive format.
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* Bit 3 is 1 Pixel Data is in alternate pixel format.
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* Bit 4 is 0 Pixel Data is to or from the display frame buffer.
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* Bit 4 is 1 Pixel Data is to or from the camera.
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* Bit 5 is 0 pixel data contains the next consecutive row of pixels.
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* Bit 5 is 1 X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
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* X Start, and Y Start parameters are not defined and
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* shall be ignored by the client.
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* Bits [7:6] = 01 Pixel data is written to the offline image buffer.
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* Bits [7:6] = 00 Pixel data is written to the buffer to refresh display.
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* Bits [7:6] = 11 Pixel data is written to all image buffers.
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* Bits [7:6] = 10 Invalid. Reserved for future use.
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* Bits 8 through 11 alternate display number.
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* Bits 12 through 14 are reserved for future use and shall be set to zero.
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* Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
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*/
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uint16_t x_left_edge;
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uint16_t y_top_edge;
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/* X,Y coordinate of the top left edge of the screen window */
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uint16_t x_right_edge;
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uint16_t y_bottom_edge;
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/* X,Y coordinate of the bottom right edge of the window being
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* updated. */
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uint16_t x_start;
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uint16_t y_start;
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/* (X Start, Y Start) is the first pixel in the Pixel Data field
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* below. */
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uint16_t pixel_count;
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/* number of pixels in the Pixel Data field below. */
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uint16_t parameter_CRC;
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/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
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uint16_t reserved;
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/* 16-bit variable to make structure align on 4 byte boundary */
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};
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#define TYPE_VIDEO_STREAM 16
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#define TYPE_CLIENT_CAPS 66
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#define TYPE_REGISTER_ACCESS 146
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#define TYPE_CLIENT_STATUS 70
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struct __attribute__((packed)) mddi_register_access {
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uint16_t length;
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uint16_t type; /* 146 */
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uint16_t client_id;
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uint16_t read_write_info;
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/* Bits 13:0 a 14-bit unsigned integer that specifies the number of
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* 32-bit Register Data List items to be transferred in the
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* Register Data List field.
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* Bits[15:14] = 00 Write to register(s);
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* Bits[15:14] = 10 Read from register(s);
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* Bits[15:14] = 11 Response to a Read.
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* Bits[15:14] = 01 this value is reserved for future use. */
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#define MDDI_WRITE (0 << 14)
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#define MDDI_READ (2 << 14)
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#define MDDI_READ_RESP (3 << 14)
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uint32_t register_address;
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/* the register address that is to be written to or read from. */
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uint16_t crc16;
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uint32_t register_data_list;
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/* list of 4-byte register data values for/from client registers */
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};
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struct __attribute__((packed)) mddi_llentry {
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uint16_t flags;
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uint16_t header_count;
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uint16_t data_count;
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dma_addr_t data; /* 32 bit */
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struct mddi_llentry *next;
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uint16_t reserved;
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union {
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struct mddi_video_stream v;
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struct mddi_register_access r;
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uint32_t _[12];
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} u;
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};
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#endif
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