linux_dsm_epyc7002/drivers/net/can/c_can
Thor Thayer 427460c83c can: c_can: Update D_CAN TX and RX functions to 32 bit - fix Altera Cyclone access
When testing CAN write floods on Altera's CycloneV, the first 2 bytes
are sometimes 0x00, 0x00 or corrupted instead of the values sent. Also
observed bytes 4 & 5 were corrupted in some cases.

The D_CAN Data registers are 32 bits and changing from 16 bit writes to
32 bit writes fixes the problem.

Testing performed on Altera CycloneV (D_CAN).  Requesting tests on other
C_CAN & D_CAN platforms.

Reported-by: Richard Andrysek <richard.andrysek@gomtec.de>
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2016-06-20 09:32:40 +02:00
..
c_can_pci.c
c_can_platform.c can: c_can: use regmap_update_bits() to modify RAMINIT register 2015-01-15 16:58:00 +01:00
c_can.c can: c_can: Update D_CAN TX and RX functions to 32 bit - fix Altera Cyclone access 2016-06-20 09:32:40 +02:00
c_can.h can: c_can: Add support for START pulse in RAMINIT sequence 2014-11-17 12:19:27 +01:00
Kconfig
Makefile