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5070fb14a0
When trying to set the ICST 307 clock to 25174000 Hz I ran into this arithmetic error: the icst_hz_to_vco() correctly figure out DIVIDE=2, RDW=100 and VDW=99 yielding a frequency of 25174000 Hz out of the VCO. (I replicated the icst_hz() function in a spreadsheet to verify this.) However, when I called icst_hz() on these VCO settings it would instead return 4122709 Hz. This causes an error in the common clock driver for ICST as the common clock framework will call .round_rate() on the clock which will utilize icst_hz_to_vco() followed by icst_hz() suggesting the erroneous frequency, and then the clock gets set to this. The error did not manifest in the old clock framework since this high frequency was only used by the CLCD, which calls clk_set_rate() without first calling clk_round_rate() and since the old clock framework would not call clk_round_rate() before setting the frequency, the correct values propagated into the VCO. After some experimenting I figured out that it was due to a simple arithmetic overflow: the divisor for 24Mhz reference frequency as reference becomes 24000000*2*(99+8)=0x132212400 and the "1" in bit 32 overflows and is lost. But introducing an explicit 64-by-32 bit do_div() and casting the divisor into (u64) we get the right frequency back, and the right frequency gets set. Tested on the ARM Versatile. Cc: stable@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/*
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* linux/arch/arm/common/icst307.c
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Support functions for calculating clocks/divisors for the ICST307
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* clock generators. See http://www.idt.com/ for more information
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* on these devices.
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*
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* This is an almost identical implementation to the ICST525 clock generator.
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* The s2div and idx2s files are different
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <asm/div64.h>
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#include <asm/hardware/icst.h>
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/*
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* Divisors for each OD setting.
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*/
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const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
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const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
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EXPORT_SYMBOL(icst307_s2div);
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EXPORT_SYMBOL(icst525_s2div);
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unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
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{
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u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
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u32 divisor = (vco.r + 2) * p->s2div[vco.s];
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do_div(dividend, divisor);
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return (unsigned long)dividend;
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}
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EXPORT_SYMBOL(icst_hz);
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/*
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* Ascending divisor S values.
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*/
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const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
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const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
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EXPORT_SYMBOL(icst307_idx2s);
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EXPORT_SYMBOL(icst525_idx2s);
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struct icst_vco
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icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
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{
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struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
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unsigned long f;
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unsigned int i = 0, rd, best = (unsigned int)-1;
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/*
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* First, find the PLL output divisor such
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* that the PLL output is within spec.
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*/
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do {
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f = freq * p->s2div[p->idx2s[i]];
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if (f > p->vco_min && f <= p->vco_max)
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break;
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} while (i < 8);
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if (i >= 8)
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return vco;
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vco.s = p->idx2s[i];
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/*
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* Now find the closest divisor combination
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* which gives a PLL output of 'f'.
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*/
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for (rd = p->rd_min; rd <= p->rd_max; rd++) {
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unsigned long fref_div, f_pll;
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unsigned int vd;
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int f_diff;
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fref_div = (2 * p->ref) / rd;
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vd = (f + fref_div / 2) / fref_div;
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if (vd < p->vd_min || vd > p->vd_max)
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continue;
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f_pll = fref_div * vd;
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f_diff = f_pll - f;
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if (f_diff < 0)
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f_diff = -f_diff;
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if ((unsigned)f_diff < best) {
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vco.v = vd - 8;
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vco.r = rd - 2;
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if (f_diff == 0)
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break;
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best = f_diff;
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}
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}
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return vco;
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}
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EXPORT_SYMBOL(icst_hz_to_vco);
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