Michael Neuling 506e70d132 powerpc/pmu: Fix order of interpreting BHRB target entries ... The current Branch History Rolling Buffer (BHRB) code misinterprets the order of entries in the hardware buffer. It assumes that a branch target address will be read _after_ its corresponding branch. In reality the branch target comes before (lower mfbhrb entry) it's corresponding branch. This is a rewrite of the code to take this into account. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2013-05-14 16:00:22 +10:00
..
bhrb.S	powerpc/perf: Add basic assembly code to read BHRB entries on POWER8	2013-04-26 16:11:11 +10:00
callchain.c	powerpc/perf: Use perf_instruction_pointer in callchains	2012-07-10 19:18:46 +10:00
core-book3s.c	powerpc/pmu: Fix order of interpreting BHRB target entries	2013-05-14 16:00:22 +10:00
core-fsl-emb.c	perf: Pass last sampling period to perf_sample_data_init()	2012-05-09 15:23:12 +02:00
e500-pmu.c	powerpc/perf: Add stalled-cycles events	2013-01-10 17:00:56 +11:00
Makefile	powerpc/perf: Add basic assembly code to read BHRB entries on POWER8	2013-04-26 16:11:11 +10:00
mpc7450-pmu.c	powerpc/perf: Move perf core & PMU code into a subdirectory	2012-02-23 10:50:04 +11:00
power4-pmu.c	powerpc/perf: Fix instruction address sampling on 970 and Power4	2012-03-28 11:33:24 +11:00
power5-pmu.c	powerpc/perf: Add an explict flag indicating presence of SLOT field	2013-04-26 16:11:07 +10:00
power5+-pmu.c	powerpc/perf: Add an explict flag indicating presence of SLOT field	2013-04-26 16:11:07 +10:00
power6-pmu.c	powerpc/perf: Move perf core & PMU code into a subdirectory	2012-02-23 10:50:04 +11:00
power7-pmu.c	perf/POWER7: Create a sysfs format entry for Power7 events	2013-03-13 17:01:04 -03:00
power8-pmu.c	powerpc/perf: Define BHRB generic functions, data and flags for POWER8	2013-04-26 16:13:01 +10:00
ppc970-pmu.c	powerpc/perf: Fix instruction address sampling on 970 and Power4	2012-03-28 11:33:24 +11:00