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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5904a7f916
Patch from Vitaly Wool Convert pnx4008 chip support to use generic irq subsystem Signed-off-by: Vitaly Wool <vitalywool@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* arch/arm/mach-pnx4008/time.c
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*
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* PNX4008 Timers
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*
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* Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/kallsyms.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/irq.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/leds.h>
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#include <asm/mach/time.h>
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#include <asm/errno.h>
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/*! Note: all timers are UPCOUNTING */
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/*!
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* Returns number of us since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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*/
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static unsigned long pnx4008_gettimeoffset(void)
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{
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u32 ticks_to_match =
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__raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
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u32 elapsed = LATCH - ticks_to_match;
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return (elapsed * (tick_nsec / 1000)) / LATCH;
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}
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/*!
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* IRQ handler for the timer
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*/
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static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
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write_seqlock(&xtime_lock);
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do {
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timer_tick(regs);
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/*
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* this algorithm takes care of possible delay
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* for this interrupt handling longer than a normal
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* timer period
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*/
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__raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
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HSTIM_MATCH0);
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__raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
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/*
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* The goal is to keep incrementing HSTIM_MATCH0
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* register until HSTIM_MATCH0 indicates time after
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* what HSTIM_COUNTER indicates.
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*/
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} while ((signed)
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(__raw_readl(HSTIM_MATCH0) -
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__raw_readl(HSTIM_COUNTER)) < 0);
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write_sequnlock(&xtime_lock);
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}
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return IRQ_HANDLED;
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}
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static struct irqaction pnx4008_timer_irq = {
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.name = "PNX4008 Tick Timer",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = pnx4008_timer_interrupt
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};
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/*!
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* Set up timer and timer interrupt.
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*/
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static __init void pnx4008_setup_timer(void)
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{
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__raw_writel(RESET_COUNT, MSTIM_CTRL);
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while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
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__raw_writel(0, MSTIM_CTRL); /* stop the timer */
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__raw_writel(0, MSTIM_MCTRL);
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__raw_writel(RESET_COUNT, HSTIM_CTRL);
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while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
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__raw_writel(0, HSTIM_CTRL);
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__raw_writel(0, HSTIM_MCTRL);
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__raw_writel(0, HSTIM_CCR);
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__raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
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__raw_writel(LATCH, HSTIM_MATCH0);
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__raw_writel(MR0_INT, HSTIM_MCTRL);
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setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
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__raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
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}
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/* Timer Clock Control in PM register */
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#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
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#define WATCHDOG_CLK_EN 1
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#define TIMER_CLK_EN 2 /* HS and MS timers? */
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static u32 timclk_ctrl_reg_save;
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void pnx4008_timer_suspend(void)
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{
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timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
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__raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
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}
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void pnx4008_timer_resume(void)
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{
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__raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
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}
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struct sys_timer pnx4008_timer = {
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.init = pnx4008_setup_timer,
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.offset = pnx4008_gettimeoffset,
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.suspend = pnx4008_timer_suspend,
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.resume = pnx4008_timer_resume,
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};
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