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8ec6d93508
Add support for the Lantiq XWAY family of Mips24KEc SoCs.
* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)
The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.
The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function
int lq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name);
which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.
The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
40 lines
877 B
C
40 lines
877 B
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <lantiq_soc.h>
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#include "../prom.h"
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#define SOC_AMAZON_SE "Amazon_SE"
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#define PART_SHIFT 12
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#define PART_MASK 0x0FFFFFFF
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#define REV_SHIFT 28
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#define REV_MASK 0xF0000000
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void __init ltq_soc_detect(struct ltq_soc_info *i)
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{
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i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
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i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
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switch (i->partnum) {
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case SOC_ID_AMAZON_SE:
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i->name = SOC_AMAZON_SE;
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i->type = SOC_TYPE_AMAZON_SE;
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break;
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default:
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unreachable();
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break;
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}
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}
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