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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dcdecdcfe1
Recently genphy_read_abilities() has been added that dynamically detects clause 22 PHY abilities. I *think* this detection should work with all supported PHY's, at least for the ones with basic features sets, i.e. PHY_BASIC_FEATURES and PHY_GBIT_FEATURES. So let's remove setting these features explicitly and rely on phylib feature detection. I don't have access to most of these PHY's, therefore I'd appreciate regression testing. v2: - make the feature constant a comment so that readers know which features are supported by the respective PHY Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* drivers/net/phy/et1011c.c
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*
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* Driver for LSI ET1011C PHYs
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*
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* Author: Chaithrika U S
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*
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* Copyright (c) 2008 Texas Instruments
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <asm/irq.h>
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#define ET1011C_STATUS_REG (0x1A)
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#define ET1011C_CONFIG_REG (0x16)
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#define ET1011C_SPEED_MASK (0x0300)
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#define ET1011C_GIGABIT_SPEED (0x0200)
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#define ET1011C_TX_FIFO_MASK (0x3000)
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#define ET1011C_TX_FIFO_DEPTH_8 (0x0000)
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#define ET1011C_TX_FIFO_DEPTH_16 (0x1000)
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#define ET1011C_INTERFACE_MASK (0x0007)
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#define ET1011C_GMII_INTERFACE (0x0002)
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#define ET1011C_SYS_CLK_EN (0x01 << 4)
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MODULE_DESCRIPTION("LSI ET1011C PHY driver");
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MODULE_AUTHOR("Chaithrika U S");
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MODULE_LICENSE("GPL");
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static int et1011c_config_aneg(struct phy_device *phydev)
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{
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int ctl = 0;
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ctl = phy_read(phydev, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
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BMCR_ANENABLE);
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/* First clear the PHY */
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phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
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return genphy_config_aneg(phydev);
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}
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static int et1011c_read_status(struct phy_device *phydev)
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{
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int ret;
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u32 val;
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static int speed;
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ret = genphy_read_status(phydev);
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if (speed != phydev->speed) {
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speed = phydev->speed;
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val = phy_read(phydev, ET1011C_STATUS_REG);
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if ((val & ET1011C_SPEED_MASK) ==
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ET1011C_GIGABIT_SPEED) {
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val = phy_read(phydev, ET1011C_CONFIG_REG);
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val &= ~ET1011C_TX_FIFO_MASK;
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phy_write(phydev, ET1011C_CONFIG_REG, val\
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| ET1011C_GMII_INTERFACE\
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| ET1011C_SYS_CLK_EN\
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| ET1011C_TX_FIFO_DEPTH_16);
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}
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}
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return ret;
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}
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static struct phy_driver et1011c_driver[] = { {
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.phy_id = 0x0282f014,
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.name = "ET1011C",
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.phy_id_mask = 0xfffffff0,
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/* PHY_GBIT_FEATURES */
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.config_aneg = et1011c_config_aneg,
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.read_status = et1011c_read_status,
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} };
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module_phy_driver(et1011c_driver);
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static struct mdio_device_id __maybe_unused et1011c_tbl[] = {
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{ 0x0282f014, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, et1011c_tbl);
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