mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
6c58f25e69
The argument passed to cmpxchg is not guaranteed to be sign extended, but lr.w sign extends on RV64I. This makes cmpxchg fail on clang built kernels when __old is negative. To fix this, we just cast __old to long which sign extends on RV64I. With this fix, clang built RISC-V kernels now boot. Link: https://github.com/ClangBuiltLinux/linux/issues/867 Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
376 lines
9.2 KiB
C
376 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CMPXCHG_H
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#define _ASM_RISCV_CMPXCHG_H
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#include <linux/bug.h>
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#include <asm/barrier.h>
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#include <asm/fence.h>
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#define __xchg_relaxed(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(new) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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" amoswap.w %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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" amoswap.d %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define xchg_relaxed(ptr, x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg_relaxed((ptr), \
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_x_, sizeof(*(ptr))); \
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})
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#define __xchg_acquire(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(new) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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" amoswap.w %0, %2, %1\n" \
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RISCV_ACQUIRE_BARRIER \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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" amoswap.d %0, %2, %1\n" \
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RISCV_ACQUIRE_BARRIER \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define xchg_acquire(ptr, x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg_acquire((ptr), \
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_x_, sizeof(*(ptr))); \
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})
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#define __xchg_release(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(new) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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RISCV_RELEASE_BARRIER \
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" amoswap.w %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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RISCV_RELEASE_BARRIER \
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" amoswap.d %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define xchg_release(ptr, x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg_release((ptr), \
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_x_, sizeof(*(ptr))); \
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})
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#define __xchg(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(new) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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" amoswap.w.aqrl %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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" amoswap.d.aqrl %0, %2, %1\n" \
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: "=r" (__ret), "+A" (*__ptr) \
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: "r" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define xchg(ptr, x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr))); \
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})
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#define xchg32(ptr, x) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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xchg((ptr), (x)); \
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})
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#define xchg64(ptr, x) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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xchg((ptr), (x)); \
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})
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __cmpxchg_relaxed(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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"0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" ((long)__old), "rJ" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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"0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" (__old), "rJ" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define cmpxchg_relaxed(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg_relaxed((ptr), \
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_o_, _n_, sizeof(*(ptr))); \
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})
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#define __cmpxchg_acquire(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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"0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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RISCV_ACQUIRE_BARRIER \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" ((long)__old), "rJ" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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"0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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RISCV_ACQUIRE_BARRIER \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" (__old), "rJ" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define cmpxchg_acquire(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg_acquire((ptr), \
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_o_, _n_, sizeof(*(ptr))); \
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})
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#define __cmpxchg_release(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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RISCV_RELEASE_BARRIER \
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"0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" ((long)__old), "rJ" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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RISCV_RELEASE_BARRIER \
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"0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" (__old), "rJ" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define cmpxchg_release(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg_release((ptr), \
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_o_, _n_, sizeof(*(ptr))); \
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})
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#define __cmpxchg(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__ ( \
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"0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" ((long)__old), "rJ" (__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__ ( \
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"0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \
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: "rJ" (__old), "rJ" (__new) \
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: "memory"); \
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break; \
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default: \
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BUILD_BUG(); \
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} \
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__ret; \
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})
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), \
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_o_, _n_, sizeof(*(ptr))); \
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})
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#define cmpxchg_local(ptr, o, n) \
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(__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr))))
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#define cmpxchg32(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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cmpxchg((ptr), (o), (n)); \
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})
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#define cmpxchg32_local(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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cmpxchg_relaxed((ptr), (o), (n)) \
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})
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#define cmpxchg64(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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cmpxchg((ptr), (o), (n)); \
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})
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#define cmpxchg64_local(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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cmpxchg_relaxed((ptr), (o), (n)); \
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})
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#endif /* _ASM_RISCV_CMPXCHG_H */
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