mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 22:05:23 +07:00
b86ecb3766
Add a vcpu_get_regs() and vcpu_set_regs() callbacks for loading and restoring context which may be in hardware registers. This may include floating point and MIPS SIMD Architecture (MSA) state which may be accessed directly by the guest (but restored lazily by the hypervisor), and also dedicated guest registers as provided by the VZ ASE. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
817 lines
20 KiB
C
817 lines
20 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
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* TLB handlers run from KSEG0
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/kvm_host.h>
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#include <linux/srcu.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/tlb.h>
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#undef CONFIG_MIPS_MT
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#include <asm/r4kcache.h>
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#define CONFIG_MIPS_MT
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#define KVM_GUEST_PC_TLB 0
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#define KVM_GUEST_SP_TLB 1
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#define PRIx64 "llx"
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atomic_t kvm_mips_instance;
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EXPORT_SYMBOL(kvm_mips_instance);
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/* These function pointers are initialized once the KVM module is loaded */
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pfn_t (*kvm_mips_gfn_to_pfn)(struct kvm *kvm, gfn_t gfn);
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EXPORT_SYMBOL(kvm_mips_gfn_to_pfn);
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void (*kvm_mips_release_pfn_clean)(pfn_t pfn);
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EXPORT_SYMBOL(kvm_mips_release_pfn_clean);
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bool (*kvm_mips_is_error_pfn)(pfn_t pfn);
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EXPORT_SYMBOL(kvm_mips_is_error_pfn);
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uint32_t kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.guest_kernel_asid[smp_processor_id()] & ASID_MASK;
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}
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uint32_t kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.guest_user_asid[smp_processor_id()] & ASID_MASK;
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}
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inline uint32_t kvm_mips_get_commpage_asid(struct kvm_vcpu *vcpu)
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{
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return vcpu->kvm->arch.commpage_tlb;
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}
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/* Structure defining an tlb entry data set. */
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void kvm_mips_dump_host_tlbs(void)
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{
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unsigned long old_entryhi;
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unsigned long old_pagemask;
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struct kvm_mips_tlb tlb;
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unsigned long flags;
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int i;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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kvm_info("HOST TLBs:\n");
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kvm_info("ASID: %#lx\n", read_c0_entryhi() & ASID_MASK);
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for (i = 0; i < current_cpu_data.tlbsize; i++) {
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write_c0_index(i);
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mtc0_tlbw_hazard();
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tlb_read();
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tlbw_use_hazard();
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tlb.tlb_hi = read_c0_entryhi();
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tlb.tlb_lo0 = read_c0_entrylo0();
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tlb.tlb_lo1 = read_c0_entrylo1();
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tlb.tlb_mask = read_c0_pagemask();
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
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i, tlb.tlb_hi);
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kvm_info("Lo0=0x%09" PRIx64 " %c%c attr %lx ",
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(uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
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(tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo0 >> 3) & 7);
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kvm_info("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n",
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(uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
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(tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
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}
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write_c0_entryhi(old_entryhi);
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write_c0_pagemask(old_pagemask);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(kvm_mips_dump_host_tlbs);
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void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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struct kvm_mips_tlb tlb;
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int i;
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kvm_info("Guest TLBs:\n");
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kvm_info("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0));
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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tlb = vcpu->arch.guest_tlb[i];
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
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i, tlb.tlb_hi);
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kvm_info("Lo0=0x%09" PRIx64 " %c%c attr %lx ",
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(uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
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(tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo0 >> 3) & 7);
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kvm_info("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n",
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(uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
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(tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
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(tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
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(tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
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}
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}
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EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs);
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static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn)
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{
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int srcu_idx, err = 0;
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pfn_t pfn;
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if (kvm->arch.guest_pmap[gfn] != KVM_INVALID_PAGE)
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return 0;
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srcu_idx = srcu_read_lock(&kvm->srcu);
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pfn = kvm_mips_gfn_to_pfn(kvm, gfn);
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if (kvm_mips_is_error_pfn(pfn)) {
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kvm_err("Couldn't get pfn for gfn %#" PRIx64 "!\n", gfn);
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err = -EFAULT;
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goto out;
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}
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kvm->arch.guest_pmap[gfn] = pfn;
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out:
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return err;
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}
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/* Translate guest KSEG0 addresses to Host PA */
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unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
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unsigned long gva)
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{
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gfn_t gfn;
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uint32_t offset = gva & ~PAGE_MASK;
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struct kvm *kvm = vcpu->kvm;
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if (KVM_GUEST_KSEGX(gva) != KVM_GUEST_KSEG0) {
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kvm_err("%s/%p: Invalid gva: %#lx\n", __func__,
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__builtin_return_address(0), gva);
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return KVM_INVALID_PAGE;
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}
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gfn = (KVM_GUEST_CPHYSADDR(gva) >> PAGE_SHIFT);
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if (gfn >= kvm->arch.guest_pmap_npages) {
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kvm_err("%s: Invalid gfn: %#llx, GVA: %#lx\n", __func__, gfn,
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gva);
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return KVM_INVALID_PAGE;
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}
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if (kvm_mips_map_page(vcpu->kvm, gfn) < 0)
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return KVM_INVALID_ADDR;
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return (kvm->arch.guest_pmap[gfn] << PAGE_SHIFT) + offset;
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}
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EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa);
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/* XXXKYMA: Must be called with interrupts disabled */
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/* set flush_dcache_mask == 0 if no dcache flush required */
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int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
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unsigned long entrylo0, unsigned long entrylo1,
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int flush_dcache_mask)
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{
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unsigned long flags;
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unsigned long old_entryhi;
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int idx;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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write_c0_entryhi(entryhi);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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if (idx > current_cpu_data.tlbsize) {
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kvm_err("%s: Invalid Index: %d\n", __func__, idx);
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kvm_mips_dump_host_tlbs();
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local_irq_restore(flags);
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return -1;
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}
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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mtc0_tlbw_hazard();
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if (idx < 0)
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tlb_write_random();
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else
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tlb_write_indexed();
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tlbw_use_hazard();
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kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0(R): 0x%08lx, entrylo1(R): 0x%08lx\n",
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vcpu->arch.pc, idx, read_c0_entryhi(),
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read_c0_entrylo0(), read_c0_entrylo1());
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/* Flush D-cache */
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if (flush_dcache_mask) {
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if (entrylo0 & MIPS3_PG_V) {
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++vcpu->stat.flush_dcache_exits;
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flush_data_cache_page((entryhi & VPN2_MASK) &
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~flush_dcache_mask);
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}
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if (entrylo1 & MIPS3_PG_V) {
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++vcpu->stat.flush_dcache_exits;
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flush_data_cache_page(((entryhi & VPN2_MASK) &
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~flush_dcache_mask) |
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(0x1 << PAGE_SHIFT));
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}
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}
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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return 0;
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}
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/* XXXKYMA: Must be called with interrupts disabled */
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int kvm_mips_handle_kseg0_tlb_fault(unsigned long badvaddr,
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struct kvm_vcpu *vcpu)
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{
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gfn_t gfn;
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pfn_t pfn0, pfn1;
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unsigned long vaddr = 0;
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unsigned long entryhi = 0, entrylo0 = 0, entrylo1 = 0;
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int even;
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struct kvm *kvm = vcpu->kvm;
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const int flush_dcache_mask = 0;
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if (KVM_GUEST_KSEGX(badvaddr) != KVM_GUEST_KSEG0) {
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kvm_err("%s: Invalid BadVaddr: %#lx\n", __func__, badvaddr);
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kvm_mips_dump_host_tlbs();
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return -1;
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}
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gfn = (KVM_GUEST_CPHYSADDR(badvaddr) >> PAGE_SHIFT);
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if (gfn >= kvm->arch.guest_pmap_npages) {
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kvm_err("%s: Invalid gfn: %#llx, BadVaddr: %#lx\n", __func__,
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gfn, badvaddr);
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kvm_mips_dump_host_tlbs();
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return -1;
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}
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even = !(gfn & 0x1);
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vaddr = badvaddr & (PAGE_MASK << 1);
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if (kvm_mips_map_page(vcpu->kvm, gfn) < 0)
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return -1;
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if (kvm_mips_map_page(vcpu->kvm, gfn ^ 0x1) < 0)
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return -1;
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if (even) {
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pfn0 = kvm->arch.guest_pmap[gfn];
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pfn1 = kvm->arch.guest_pmap[gfn ^ 0x1];
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} else {
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pfn0 = kvm->arch.guest_pmap[gfn ^ 0x1];
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pfn1 = kvm->arch.guest_pmap[gfn];
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}
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entryhi = (vaddr | kvm_mips_get_kernel_asid(vcpu));
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entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |
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(1 << 2) | (0x1 << 1);
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entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) |
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(1 << 2) | (0x1 << 1);
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return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1,
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flush_dcache_mask);
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}
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EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault);
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int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
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struct kvm_vcpu *vcpu)
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{
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pfn_t pfn0, pfn1;
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unsigned long flags, old_entryhi = 0, vaddr = 0;
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unsigned long entrylo0 = 0, entrylo1 = 0;
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pfn0 = CPHYSADDR(vcpu->arch.kseg0_commpage) >> PAGE_SHIFT;
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pfn1 = 0;
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entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |
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(1 << 2) | (0x1 << 1);
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entrylo1 = 0;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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vaddr = badvaddr & (PAGE_MASK << 1);
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write_c0_entryhi(vaddr | kvm_mips_get_kernel_asid(vcpu));
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mtc0_tlbw_hazard();
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write_c0_entrylo0(entrylo0);
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mtc0_tlbw_hazard();
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write_c0_entrylo1(entrylo1);
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mtc0_tlbw_hazard();
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write_c0_index(kvm_mips_get_commpage_asid(vcpu));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0 (R): 0x%08lx, entrylo1(R): 0x%08lx\n",
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vcpu->arch.pc, read_c0_index(), read_c0_entryhi(),
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read_c0_entrylo0(), read_c0_entrylo1());
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault);
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int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
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struct kvm_mips_tlb *tlb,
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unsigned long *hpa0,
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unsigned long *hpa1)
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{
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unsigned long entryhi = 0, entrylo0 = 0, entrylo1 = 0;
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struct kvm *kvm = vcpu->kvm;
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pfn_t pfn0, pfn1;
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if ((tlb->tlb_hi & VPN2_MASK) == 0) {
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pfn0 = 0;
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pfn1 = 0;
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} else {
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0)
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>> PAGE_SHIFT) < 0)
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return -1;
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if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1)
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>> PAGE_SHIFT) < 0)
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return -1;
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pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0)
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>> PAGE_SHIFT];
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pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1)
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>> PAGE_SHIFT];
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}
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if (hpa0)
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*hpa0 = pfn0 << PAGE_SHIFT;
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if (hpa1)
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*hpa1 = pfn1 << PAGE_SHIFT;
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/* Get attributes from the Guest TLB */
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entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ?
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kvm_mips_get_kernel_asid(vcpu) :
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kvm_mips_get_user_asid(vcpu));
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entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) |
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(tlb->tlb_lo0 & MIPS3_PG_D) | (tlb->tlb_lo0 & MIPS3_PG_V);
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entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) |
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(tlb->tlb_lo1 & MIPS3_PG_D) | (tlb->tlb_lo1 & MIPS3_PG_V);
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kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc,
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tlb->tlb_lo0, tlb->tlb_lo1);
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return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1,
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tlb->tlb_mask);
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}
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EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault);
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int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
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{
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int i;
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int index = -1;
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struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb;
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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if (TLB_HI_VPN2_HIT(tlb[i], entryhi) &&
|
|
TLB_HI_ASID_HIT(tlb[i], entryhi)) {
|
|
index = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
|
|
__func__, entryhi, index, tlb[i].tlb_lo0, tlb[i].tlb_lo1);
|
|
|
|
return index;
|
|
}
|
|
EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup);
|
|
|
|
int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr)
|
|
{
|
|
unsigned long old_entryhi, flags;
|
|
int idx;
|
|
|
|
local_irq_save(flags);
|
|
|
|
old_entryhi = read_c0_entryhi();
|
|
|
|
if (KVM_GUEST_KERNEL_MODE(vcpu))
|
|
write_c0_entryhi((vaddr & VPN2_MASK) |
|
|
kvm_mips_get_kernel_asid(vcpu));
|
|
else {
|
|
write_c0_entryhi((vaddr & VPN2_MASK) |
|
|
kvm_mips_get_user_asid(vcpu));
|
|
}
|
|
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_probe();
|
|
tlb_probe_hazard();
|
|
idx = read_c0_index();
|
|
|
|
/* Restore old ASID */
|
|
write_c0_entryhi(old_entryhi);
|
|
mtc0_tlbw_hazard();
|
|
tlbw_use_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
|
|
kvm_debug("Host TLB lookup, %#lx, idx: %2d\n", vaddr, idx);
|
|
|
|
return idx;
|
|
}
|
|
EXPORT_SYMBOL(kvm_mips_host_tlb_lookup);
|
|
|
|
int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va)
|
|
{
|
|
int idx;
|
|
unsigned long flags, old_entryhi;
|
|
|
|
local_irq_save(flags);
|
|
|
|
old_entryhi = read_c0_entryhi();
|
|
|
|
write_c0_entryhi((va & VPN2_MASK) | kvm_mips_get_user_asid(vcpu));
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_probe();
|
|
tlb_probe_hazard();
|
|
idx = read_c0_index();
|
|
|
|
if (idx >= current_cpu_data.tlbsize)
|
|
BUG();
|
|
|
|
if (idx > 0) {
|
|
write_c0_entryhi(UNIQUE_ENTRYHI(idx));
|
|
mtc0_tlbw_hazard();
|
|
|
|
write_c0_entrylo0(0);
|
|
mtc0_tlbw_hazard();
|
|
|
|
write_c0_entrylo1(0);
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_write_indexed();
|
|
mtc0_tlbw_hazard();
|
|
}
|
|
|
|
write_c0_entryhi(old_entryhi);
|
|
mtc0_tlbw_hazard();
|
|
tlbw_use_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
|
|
if (idx > 0)
|
|
kvm_debug("%s: Invalidated entryhi %#lx @ idx %d\n", __func__,
|
|
(va & VPN2_MASK) | kvm_mips_get_user_asid(vcpu), idx);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(kvm_mips_host_tlb_inv);
|
|
|
|
/* XXXKYMA: Fix Guest USER/KERNEL no longer share the same ASID */
|
|
int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index)
|
|
{
|
|
unsigned long flags, old_entryhi;
|
|
|
|
if (index >= current_cpu_data.tlbsize)
|
|
BUG();
|
|
|
|
local_irq_save(flags);
|
|
|
|
old_entryhi = read_c0_entryhi();
|
|
|
|
write_c0_entryhi(UNIQUE_ENTRYHI(index));
|
|
mtc0_tlbw_hazard();
|
|
|
|
write_c0_index(index);
|
|
mtc0_tlbw_hazard();
|
|
|
|
write_c0_entrylo0(0);
|
|
mtc0_tlbw_hazard();
|
|
|
|
write_c0_entrylo1(0);
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_write_indexed();
|
|
mtc0_tlbw_hazard();
|
|
tlbw_use_hazard();
|
|
|
|
write_c0_entryhi(old_entryhi);
|
|
mtc0_tlbw_hazard();
|
|
tlbw_use_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void kvm_mips_flush_host_tlb(int skip_kseg0)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long old_entryhi, entryhi;
|
|
unsigned long old_pagemask;
|
|
int entry = 0;
|
|
int maxentry = current_cpu_data.tlbsize;
|
|
|
|
local_irq_save(flags);
|
|
|
|
old_entryhi = read_c0_entryhi();
|
|
old_pagemask = read_c0_pagemask();
|
|
|
|
/* Blast 'em all away. */
|
|
for (entry = 0; entry < maxentry; entry++) {
|
|
write_c0_index(entry);
|
|
mtc0_tlbw_hazard();
|
|
|
|
if (skip_kseg0) {
|
|
tlb_read();
|
|
tlbw_use_hazard();
|
|
|
|
entryhi = read_c0_entryhi();
|
|
|
|
/* Don't blow away guest kernel entries */
|
|
if (KVM_GUEST_KSEGX(entryhi) == KVM_GUEST_KSEG0)
|
|
continue;
|
|
}
|
|
|
|
/* Make sure all entries differ. */
|
|
write_c0_entryhi(UNIQUE_ENTRYHI(entry));
|
|
mtc0_tlbw_hazard();
|
|
write_c0_entrylo0(0);
|
|
mtc0_tlbw_hazard();
|
|
write_c0_entrylo1(0);
|
|
mtc0_tlbw_hazard();
|
|
|
|
tlb_write_indexed();
|
|
mtc0_tlbw_hazard();
|
|
}
|
|
|
|
tlbw_use_hazard();
|
|
|
|
write_c0_entryhi(old_entryhi);
|
|
write_c0_pagemask(old_pagemask);
|
|
mtc0_tlbw_hazard();
|
|
tlbw_use_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
EXPORT_SYMBOL(kvm_mips_flush_host_tlb);
|
|
|
|
void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
|
|
struct kvm_vcpu *vcpu)
|
|
{
|
|
unsigned long asid = asid_cache(cpu);
|
|
|
|
asid += ASID_INC;
|
|
if (!(asid & ASID_MASK)) {
|
|
if (cpu_has_vtag_icache)
|
|
flush_icache_all();
|
|
|
|
kvm_local_flush_tlb_all(); /* start new asid cycle */
|
|
|
|
if (!asid) /* fix version if needed */
|
|
asid = ASID_FIRST_VERSION;
|
|
}
|
|
|
|
cpu_context(cpu, mm) = asid_cache(cpu) = asid;
|
|
}
|
|
|
|
void kvm_local_flush_tlb_all(void)
|
|
{
|
|
unsigned long flags;
|
|
unsigned long old_ctx;
|
|
int entry = 0;
|
|
|
|
local_irq_save(flags);
|
|
/* Save old context and create impossible VPN2 value */
|
|
old_ctx = read_c0_entryhi();
|
|
write_c0_entrylo0(0);
|
|
write_c0_entrylo1(0);
|
|
|
|
/* Blast 'em all away. */
|
|
while (entry < current_cpu_data.tlbsize) {
|
|
/* Make sure all entries differ. */
|
|
write_c0_entryhi(UNIQUE_ENTRYHI(entry));
|
|
write_c0_index(entry);
|
|
mtc0_tlbw_hazard();
|
|
tlb_write_indexed();
|
|
entry++;
|
|
}
|
|
tlbw_use_hazard();
|
|
write_c0_entryhi(old_ctx);
|
|
mtc0_tlbw_hazard();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
EXPORT_SYMBOL(kvm_local_flush_tlb_all);
|
|
|
|
/**
|
|
* kvm_mips_migrate_count() - Migrate timer.
|
|
* @vcpu: Virtual CPU.
|
|
*
|
|
* Migrate CP0_Count hrtimer to the current CPU by cancelling and restarting it
|
|
* if it was running prior to being cancelled.
|
|
*
|
|
* Must be called when the VCPU is migrated to a different CPU to ensure that
|
|
* timer expiry during guest execution interrupts the guest and causes the
|
|
* interrupt to be delivered in a timely manner.
|
|
*/
|
|
static void kvm_mips_migrate_count(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (hrtimer_cancel(&vcpu->arch.comparecount_timer))
|
|
hrtimer_restart(&vcpu->arch.comparecount_timer);
|
|
}
|
|
|
|
/* Restore ASID once we are scheduled back after preemption */
|
|
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|
{
|
|
unsigned long flags;
|
|
int newasid = 0;
|
|
|
|
kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu);
|
|
|
|
/* Alocate new kernel and user ASIDs if needed */
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (((vcpu->arch.
|
|
guest_kernel_asid[cpu] ^ asid_cache(cpu)) & ASID_VERSION_MASK)) {
|
|
kvm_get_new_mmu_context(&vcpu->arch.guest_kernel_mm, cpu, vcpu);
|
|
vcpu->arch.guest_kernel_asid[cpu] =
|
|
vcpu->arch.guest_kernel_mm.context.asid[cpu];
|
|
kvm_get_new_mmu_context(&vcpu->arch.guest_user_mm, cpu, vcpu);
|
|
vcpu->arch.guest_user_asid[cpu] =
|
|
vcpu->arch.guest_user_mm.context.asid[cpu];
|
|
newasid++;
|
|
|
|
kvm_debug("[%d]: cpu_context: %#lx\n", cpu,
|
|
cpu_context(cpu, current->mm));
|
|
kvm_debug("[%d]: Allocated new ASID for Guest Kernel: %#x\n",
|
|
cpu, vcpu->arch.guest_kernel_asid[cpu]);
|
|
kvm_debug("[%d]: Allocated new ASID for Guest User: %#x\n", cpu,
|
|
vcpu->arch.guest_user_asid[cpu]);
|
|
}
|
|
|
|
if (vcpu->arch.last_sched_cpu != cpu) {
|
|
kvm_debug("[%d->%d]KVM VCPU[%d] switch\n",
|
|
vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id);
|
|
/*
|
|
* Migrate the timer interrupt to the current CPU so that it
|
|
* always interrupts the guest and synchronously triggers a
|
|
* guest timer interrupt.
|
|
*/
|
|
kvm_mips_migrate_count(vcpu);
|
|
}
|
|
|
|
if (!newasid) {
|
|
/*
|
|
* If we preempted while the guest was executing, then reload
|
|
* the pre-empted ASID
|
|
*/
|
|
if (current->flags & PF_VCPU) {
|
|
write_c0_entryhi(vcpu->arch.
|
|
preempt_entryhi & ASID_MASK);
|
|
ehb();
|
|
}
|
|
} else {
|
|
/* New ASIDs were allocated for the VM */
|
|
|
|
/*
|
|
* Were we in guest context? If so then the pre-empted ASID is
|
|
* no longer valid, we need to set it to what it should be based
|
|
* on the mode of the Guest (Kernel/User)
|
|
*/
|
|
if (current->flags & PF_VCPU) {
|
|
if (KVM_GUEST_KERNEL_MODE(vcpu))
|
|
write_c0_entryhi(vcpu->arch.
|
|
guest_kernel_asid[cpu] &
|
|
ASID_MASK);
|
|
else
|
|
write_c0_entryhi(vcpu->arch.
|
|
guest_user_asid[cpu] &
|
|
ASID_MASK);
|
|
ehb();
|
|
}
|
|
}
|
|
|
|
/* restore guest state to registers */
|
|
kvm_mips_callbacks->vcpu_set_regs(vcpu);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(kvm_arch_vcpu_load);
|
|
|
|
/* ASID can change if another task is scheduled during preemption */
|
|
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
|
{
|
|
unsigned long flags;
|
|
uint32_t cpu;
|
|
|
|
local_irq_save(flags);
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
vcpu->arch.preempt_entryhi = read_c0_entryhi();
|
|
vcpu->arch.last_sched_cpu = cpu;
|
|
|
|
/* save guest state in registers */
|
|
kvm_mips_callbacks->vcpu_get_regs(vcpu);
|
|
|
|
if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) &
|
|
ASID_VERSION_MASK)) {
|
|
kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__,
|
|
cpu_context(cpu, current->mm));
|
|
drop_mmu_context(current->mm, cpu);
|
|
}
|
|
write_c0_entryhi(cpu_asid(cpu, current->mm));
|
|
ehb();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
EXPORT_SYMBOL(kvm_arch_vcpu_put);
|
|
|
|
uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu)
|
|
{
|
|
struct mips_coproc *cop0 = vcpu->arch.cop0;
|
|
unsigned long paddr, flags, vpn2, asid;
|
|
uint32_t inst;
|
|
int index;
|
|
|
|
if (KVM_GUEST_KSEGX((unsigned long) opc) < KVM_GUEST_KSEG0 ||
|
|
KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
|
|
local_irq_save(flags);
|
|
index = kvm_mips_host_tlb_lookup(vcpu, (unsigned long) opc);
|
|
if (index >= 0) {
|
|
inst = *(opc);
|
|
} else {
|
|
vpn2 = (unsigned long) opc & VPN2_MASK;
|
|
asid = kvm_read_c0_guest_entryhi(cop0) & ASID_MASK;
|
|
index = kvm_mips_guest_tlb_lookup(vcpu, vpn2 | asid);
|
|
if (index < 0) {
|
|
kvm_err("%s: get_user_failed for %p, vcpu: %p, ASID: %#lx\n",
|
|
__func__, opc, vcpu, read_c0_entryhi());
|
|
kvm_mips_dump_host_tlbs();
|
|
local_irq_restore(flags);
|
|
return KVM_INVALID_INST;
|
|
}
|
|
kvm_mips_handle_mapped_seg_tlb_fault(vcpu,
|
|
&vcpu->arch.
|
|
guest_tlb[index],
|
|
NULL, NULL);
|
|
inst = *(opc);
|
|
}
|
|
local_irq_restore(flags);
|
|
} else if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
|
|
paddr =
|
|
kvm_mips_translate_guest_kseg0_to_hpa(vcpu,
|
|
(unsigned long) opc);
|
|
inst = *(uint32_t *) CKSEG0ADDR(paddr);
|
|
} else {
|
|
kvm_err("%s: illegal address: %p\n", __func__, opc);
|
|
return KVM_INVALID_INST;
|
|
}
|
|
|
|
return inst;
|
|
}
|
|
EXPORT_SYMBOL(kvm_get_inst);
|