mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 11:57:07 +07:00
98dea8d719
Add tables to support MT7622 NAND flash controller. Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
609 lines
14 KiB
C
609 lines
14 KiB
C
/*
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* MTK ECC controller driver.
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* Copyright (C) 2016 MediaTek Inc.
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* Authors: Xiaolei Li <xiaolei.li@mediatek.com>
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* Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/mutex.h>
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#include "mtk_ecc.h"
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#define ECC_IDLE_MASK BIT(0)
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#define ECC_IRQ_EN BIT(0)
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#define ECC_PG_IRQ_SEL BIT(1)
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#define ECC_OP_ENABLE (1)
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#define ECC_OP_DISABLE (0)
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#define ECC_ENCCON (0x00)
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#define ECC_ENCCNFG (0x04)
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#define ECC_MS_SHIFT (16)
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#define ECC_ENCDIADDR (0x08)
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#define ECC_ENCIDLE (0x0C)
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#define ECC_DECCON (0x100)
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#define ECC_DECCNFG (0x104)
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#define DEC_EMPTY_EN BIT(31)
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#define DEC_CNFG_CORRECT (0x3 << 12)
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#define ECC_DECIDLE (0x10C)
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#define ECC_DECENUM0 (0x114)
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#define ECC_TIMEOUT (500000)
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#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
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#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
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struct mtk_ecc_caps {
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u32 err_mask;
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const u8 *ecc_strength;
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const u32 *ecc_regs;
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u8 num_ecc_strength;
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u8 ecc_mode_shift;
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u32 parity_bits;
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int pg_irq_sel;
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};
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struct mtk_ecc {
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struct device *dev;
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const struct mtk_ecc_caps *caps;
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void __iomem *regs;
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struct clk *clk;
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struct completion done;
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struct mutex lock;
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u32 sectors;
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u8 *eccdata;
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};
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/* ecc strength that each IP supports */
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static const u8 ecc_strength_mt2701[] = {
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4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60
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};
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static const u8 ecc_strength_mt2712[] = {
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4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
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40, 44, 48, 52, 56, 60, 68, 72, 80
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};
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static const u8 ecc_strength_mt7622[] = {
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4, 6, 8, 10, 12, 14, 16
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};
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enum mtk_ecc_regs {
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ECC_ENCPAR00,
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ECC_ENCIRQ_EN,
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ECC_ENCIRQ_STA,
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ECC_DECDONE,
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ECC_DECIRQ_EN,
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ECC_DECIRQ_STA,
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};
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static int mt2701_ecc_regs[] = {
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[ECC_ENCPAR00] = 0x10,
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[ECC_ENCIRQ_EN] = 0x80,
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[ECC_ENCIRQ_STA] = 0x84,
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[ECC_DECDONE] = 0x124,
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[ECC_DECIRQ_EN] = 0x200,
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[ECC_DECIRQ_STA] = 0x204,
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};
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static int mt2712_ecc_regs[] = {
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[ECC_ENCPAR00] = 0x300,
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[ECC_ENCIRQ_EN] = 0x80,
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[ECC_ENCIRQ_STA] = 0x84,
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[ECC_DECDONE] = 0x124,
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[ECC_DECIRQ_EN] = 0x200,
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[ECC_DECIRQ_STA] = 0x204,
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};
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static int mt7622_ecc_regs[] = {
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[ECC_ENCPAR00] = 0x10,
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[ECC_ENCIRQ_EN] = 0x30,
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[ECC_ENCIRQ_STA] = 0x34,
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[ECC_DECDONE] = 0x11c,
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[ECC_DECIRQ_EN] = 0x140,
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[ECC_DECIRQ_STA] = 0x144,
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};
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static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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enum mtk_ecc_operation op)
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{
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struct device *dev = ecc->dev;
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u32 val;
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int ret;
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ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
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val & ECC_IDLE_MASK,
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10, ECC_TIMEOUT);
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if (ret)
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dev_warn(dev, "%s NOT idle\n",
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op == ECC_ENCODE ? "encoder" : "decoder");
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}
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static irqreturn_t mtk_ecc_irq(int irq, void *id)
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{
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struct mtk_ecc *ecc = id;
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u32 dec, enc;
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dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
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& ECC_IRQ_EN;
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if (dec) {
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dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
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if (dec & ecc->sectors) {
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/*
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* Clear decode IRQ status once again to ensure that
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* there will be no extra IRQ.
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*/
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readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
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ecc->sectors = 0;
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complete(&ecc->done);
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} else {
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return IRQ_HANDLED;
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}
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} else {
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enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
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& ECC_IRQ_EN;
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if (enc)
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complete(&ecc->done);
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else
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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{
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u32 ecc_bit, dec_sz, enc_sz;
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u32 reg, i;
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for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
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if (ecc->caps->ecc_strength[i] == config->strength)
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break;
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}
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if (i == ecc->caps->num_ecc_strength) {
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dev_err(ecc->dev, "invalid ecc strength %d\n",
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config->strength);
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return -EINVAL;
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}
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ecc_bit = i;
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if (config->op == ECC_ENCODE) {
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/* configure ECC encoder (in bits) */
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enc_sz = config->len << 3;
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reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
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reg |= (enc_sz << ECC_MS_SHIFT);
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writel(reg, ecc->regs + ECC_ENCCNFG);
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if (config->mode != ECC_NFI_MODE)
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writel(lower_32_bits(config->addr),
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ecc->regs + ECC_ENCDIADDR);
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} else {
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/* configure ECC decoder (in bits) */
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dec_sz = (config->len << 3) +
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config->strength * ecc->caps->parity_bits;
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reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
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reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
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reg |= DEC_EMPTY_EN;
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writel(reg, ecc->regs + ECC_DECCNFG);
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if (config->sectors)
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ecc->sectors = 1 << (config->sectors - 1);
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}
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return 0;
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}
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void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
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int sectors)
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{
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u32 offset, i, err;
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u32 bitflips = 0;
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stats->corrected = 0;
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stats->failed = 0;
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for (i = 0; i < sectors; i++) {
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offset = (i >> 2) << 2;
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err = readl(ecc->regs + ECC_DECENUM0 + offset);
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err = err >> ((i % 4) * 8);
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err &= ecc->caps->err_mask;
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if (err == ecc->caps->err_mask) {
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/* uncorrectable errors */
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stats->failed++;
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continue;
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}
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stats->corrected += err;
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bitflips = max_t(u32, bitflips, err);
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}
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stats->bitflips = bitflips;
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}
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EXPORT_SYMBOL(mtk_ecc_get_stats);
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void mtk_ecc_release(struct mtk_ecc *ecc)
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{
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clk_disable_unprepare(ecc->clk);
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put_device(ecc->dev);
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}
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EXPORT_SYMBOL(mtk_ecc_release);
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static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
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{
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mtk_ecc_wait_idle(ecc, ECC_ENCODE);
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writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
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mtk_ecc_wait_idle(ecc, ECC_DECODE);
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writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
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}
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static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
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{
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struct platform_device *pdev;
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struct mtk_ecc *ecc;
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pdev = of_find_device_by_node(np);
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if (!pdev || !platform_get_drvdata(pdev))
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return ERR_PTR(-EPROBE_DEFER);
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get_device(&pdev->dev);
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ecc = platform_get_drvdata(pdev);
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clk_prepare_enable(ecc->clk);
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mtk_ecc_hw_init(ecc);
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return ecc;
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}
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struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
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{
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struct mtk_ecc *ecc = NULL;
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struct device_node *np;
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np = of_parse_phandle(of_node, "ecc-engine", 0);
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if (np) {
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ecc = mtk_ecc_get(np);
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of_node_put(np);
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}
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return ecc;
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}
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EXPORT_SYMBOL(of_mtk_ecc_get);
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int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
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{
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enum mtk_ecc_operation op = config->op;
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u16 reg_val;
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int ret;
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ret = mutex_lock_interruptible(&ecc->lock);
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if (ret) {
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dev_err(ecc->dev, "interrupted when attempting to lock\n");
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return ret;
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}
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mtk_ecc_wait_idle(ecc, op);
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ret = mtk_ecc_config(ecc, config);
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if (ret) {
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mutex_unlock(&ecc->lock);
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return ret;
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}
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if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
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init_completion(&ecc->done);
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reg_val = ECC_IRQ_EN;
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/*
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* For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
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* means this chip can only generate one ecc irq during page
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* read / write. If is 0, generate one ecc irq each ecc step.
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*/
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if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
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reg_val |= ECC_PG_IRQ_SEL;
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if (op == ECC_ENCODE)
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writew(reg_val, ecc->regs +
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ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
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else
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writew(reg_val, ecc->regs +
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ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
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}
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writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
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return 0;
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}
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EXPORT_SYMBOL(mtk_ecc_enable);
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void mtk_ecc_disable(struct mtk_ecc *ecc)
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{
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enum mtk_ecc_operation op = ECC_ENCODE;
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/* find out the running operation */
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if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
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op = ECC_DECODE;
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/* disable it */
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mtk_ecc_wait_idle(ecc, op);
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if (op == ECC_DECODE) {
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/*
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* Clear decode IRQ status in case there is a timeout to wait
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* decode IRQ.
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*/
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readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
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writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
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} else {
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writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
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}
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writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
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mutex_unlock(&ecc->lock);
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}
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EXPORT_SYMBOL(mtk_ecc_disable);
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int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
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{
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int ret;
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ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
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if (!ret) {
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dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
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(op == ECC_ENCODE) ? "encoder" : "decoder");
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return -ETIMEDOUT;
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}
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return 0;
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}
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EXPORT_SYMBOL(mtk_ecc_wait_done);
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int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
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u8 *data, u32 bytes)
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{
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dma_addr_t addr;
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u32 len;
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int ret;
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addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
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ret = dma_mapping_error(ecc->dev, addr);
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if (ret) {
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dev_err(ecc->dev, "dma mapping error\n");
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return -EINVAL;
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}
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config->op = ECC_ENCODE;
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config->addr = addr;
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ret = mtk_ecc_enable(ecc, config);
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if (ret) {
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dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
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return ret;
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}
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ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
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if (ret)
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goto timeout;
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mtk_ecc_wait_idle(ecc, ECC_ENCODE);
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/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
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len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
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/* write the parity bytes generated by the ECC back to temp buffer */
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__ioread32_copy(ecc->eccdata,
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ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
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round_up(len, 4));
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/* copy into possibly unaligned OOB region with actual length */
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memcpy(data + bytes, ecc->eccdata, len);
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timeout:
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dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
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mtk_ecc_disable(ecc);
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return ret;
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}
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EXPORT_SYMBOL(mtk_ecc_encode);
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void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
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{
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const u8 *ecc_strength = ecc->caps->ecc_strength;
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int i;
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for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
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if (*p <= ecc_strength[i]) {
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if (!i)
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*p = ecc_strength[i];
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else if (*p != ecc_strength[i])
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*p = ecc_strength[i - 1];
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return;
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}
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}
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*p = ecc_strength[ecc->caps->num_ecc_strength - 1];
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}
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EXPORT_SYMBOL(mtk_ecc_adjust_strength);
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unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
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{
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return ecc->caps->parity_bits;
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}
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EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
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static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
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.err_mask = 0x3f,
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.ecc_strength = ecc_strength_mt2701,
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.ecc_regs = mt2701_ecc_regs,
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.num_ecc_strength = 20,
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.ecc_mode_shift = 5,
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.parity_bits = 14,
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.pg_irq_sel = 0,
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};
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static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
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.err_mask = 0x7f,
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.ecc_strength = ecc_strength_mt2712,
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.ecc_regs = mt2712_ecc_regs,
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.num_ecc_strength = 23,
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.ecc_mode_shift = 5,
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.parity_bits = 14,
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.pg_irq_sel = 1,
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};
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static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
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.err_mask = 0x3f,
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.ecc_strength = ecc_strength_mt7622,
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.ecc_regs = mt7622_ecc_regs,
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.num_ecc_strength = 7,
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.ecc_mode_shift = 4,
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.parity_bits = 13,
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.pg_irq_sel = 0,
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};
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static const struct of_device_id mtk_ecc_dt_match[] = {
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{
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.compatible = "mediatek,mt2701-ecc",
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.data = &mtk_ecc_caps_mt2701,
|
|
}, {
|
|
.compatible = "mediatek,mt2712-ecc",
|
|
.data = &mtk_ecc_caps_mt2712,
|
|
}, {
|
|
.compatible = "mediatek,mt7622-ecc",
|
|
.data = &mtk_ecc_caps_mt7622,
|
|
},
|
|
{},
|
|
};
|
|
|
|
static int mtk_ecc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mtk_ecc *ecc;
|
|
struct resource *res;
|
|
const struct of_device_id *of_ecc_id = NULL;
|
|
u32 max_eccdata_size;
|
|
int irq, ret;
|
|
|
|
ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
|
|
if (!ecc)
|
|
return -ENOMEM;
|
|
|
|
of_ecc_id = of_match_device(mtk_ecc_dt_match, &pdev->dev);
|
|
if (!of_ecc_id)
|
|
return -ENODEV;
|
|
|
|
ecc->caps = of_ecc_id->data;
|
|
|
|
max_eccdata_size = ecc->caps->num_ecc_strength - 1;
|
|
max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
|
|
max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
|
|
max_eccdata_size = round_up(max_eccdata_size, 4);
|
|
ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
|
|
if (!ecc->eccdata)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ecc->regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(ecc->regs)) {
|
|
dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
|
|
return PTR_ERR(ecc->regs);
|
|
}
|
|
|
|
ecc->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(ecc->clk)) {
|
|
dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
|
|
return PTR_ERR(ecc->clk);
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get irq: %d\n", irq);
|
|
return irq;
|
|
}
|
|
|
|
ret = dma_set_mask(dev, DMA_BIT_MASK(32));
|
|
if (ret) {
|
|
dev_err(dev, "failed to set DMA mask\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ecc->dev = dev;
|
|
mutex_init(&ecc->lock);
|
|
platform_set_drvdata(pdev, ecc);
|
|
dev_info(dev, "probed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mtk_ecc_suspend(struct device *dev)
|
|
{
|
|
struct mtk_ecc *ecc = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(ecc->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_ecc_resume(struct device *dev)
|
|
{
|
|
struct mtk_ecc *ecc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(ecc->clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable clk\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
|
|
#endif
|
|
|
|
MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
|
|
|
|
static struct platform_driver mtk_ecc_driver = {
|
|
.probe = mtk_ecc_probe,
|
|
.driver = {
|
|
.name = "mtk-ecc",
|
|
.of_match_table = of_match_ptr(mtk_ecc_dt_match),
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.pm = &mtk_ecc_pm_ops,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mtk_ecc_driver);
|
|
|
|
MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
|
|
MODULE_DESCRIPTION("MTK Nand ECC Driver");
|
|
MODULE_LICENSE("GPL");
|