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4f56f3fdca
When the UART clock is set slightly under 1.8432MHz, the 8250 driver core doesn't permit the 115200 baud rate since it calculates the maximum frequency to pass to uart_get_baud_rate by simply dividing the uart clock by 16 which yields a value slightly under 115200, even though the frequency is close enough for the UART to operate reliably. Therefore add some tolerance in the calculation of the maximum baud rate. 1% tolerance allows for marginally slower uart clk than nominal without introducing transmission errors. Signed-off-by: James Hogan <james.hogan@imgtec.com> [pjh: Forward-port & refactor original patch; change tolerance to 1%] Signed-off-by: Peter Hurley <peter@hurleysoftware.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| 8250_accent.c | ||
| 8250_acorn.c | ||
| 8250_boca.c | ||
| 8250_core.c | ||
| 8250_dma.c | ||
| 8250_dw.c | ||
| 8250_early.c | ||
| 8250_em.c | ||
| 8250_exar_st16c554.c | ||
| 8250_fintek.c | ||
| 8250_fourport.c | ||
| 8250_fsl.c | ||
| 8250_gsc.c | ||
| 8250_hp300.c | ||
| 8250_hub6.c | ||
| 8250_ingenic.c | ||
| 8250_lpc18xx.c | ||
| 8250_mtk.c | ||
| 8250_omap.c | ||
| 8250_pci.c | ||
| 8250_pnp.c | ||
| 8250_port.c | ||
| 8250_uniphier.c | ||
| 8250.h | ||
| Kconfig | ||
| Makefile | ||
| serial_cs.c | ||