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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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952111d7db
There is no agreed-upon definition of spin_unlock_wait()'s semantics, and it appears that all callers could do just as well with a lock/unlock pair. This commit therefore removes the underlying arch-specific arch_spin_unlock_wait() for all architectures providing them. Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: <linux-arch@vger.kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Andrea Parri <parri.andrea@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Boqun Feng <boqun.feng@gmail.com>
199 lines
4.6 KiB
C
199 lines
4.6 KiB
C
/* spinlock.h: 32-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC_SPINLOCK_H
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#define __SPARC_SPINLOCK_H
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#ifndef __ASSEMBLY__
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#include <asm/psr.h>
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#include <asm/barrier.h>
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#include <asm/processor.h> /* for cpu_relax */
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#define arch_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__(
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"\n1:\n\t"
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"ldstub [%0], %%g2\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2f\n\t"
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" ldub [%0], %%g2\n\t"
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".subsection 2\n"
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"2:\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2b\n\t"
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" ldub [%0], %%g2\n\t"
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"b,a 1b\n\t"
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".previous\n"
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: /* no outputs */
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: "r" (lock)
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: "g2", "memory", "cc");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int result;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
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}
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/* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* XXX This might create some problems with my dual spinlock
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* XXX scheme, deadlocks etc. -DaveM
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*
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* Sort of like atomic_t's on Sparc, but even more clever.
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*
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* ------------------------------------
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* | 24-bit counter | wlock | arch_rwlock_t
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* ------------------------------------
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* 31 8 7 0
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*
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* wlock signifies the one writer is in or somebody is updating
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* counter. For a writer, if he successfully acquires the wlock,
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* but counter is non-zero, he has to release the lock and wait,
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* till both counter and wlock are zero.
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*
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* Unfortunately this scheme limits us to ~16,000,000 cpus.
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*/
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static inline void __arch_read_lock(arch_rwlock_t *rw)
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{
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define arch_read_lock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__arch_read_lock(lock); \
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local_irq_restore(flags); \
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} while(0)
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static inline void __arch_read_unlock(arch_rwlock_t *rw)
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{
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_exit\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define arch_read_unlock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__arch_read_unlock(lock); \
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local_irq_restore(flags); \
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} while(0)
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_write_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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*(volatile __u32 *)&lp->lock = ~0U;
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}
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static inline void arch_write_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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" st %%g0, [%0]"
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: /* no outputs */
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: "r" (lock)
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: "memory");
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int val;
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__asm__ __volatile__("ldstub [%1 + 3], %0"
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: "=r" (val)
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: "r" (&rw->lock)
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: "memory");
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if (val == 0) {
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val = rw->lock & ~0xff;
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if (val)
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((volatile u8*)&rw->lock)[3] = 0;
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else
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*(volatile u32*)&rw->lock = ~0U;
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}
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return (val == 0);
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}
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static inline int __arch_read_trylock(arch_rwlock_t *rw)
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{
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register arch_rwlock_t *lp asm("g1");
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register int res asm("o0");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_try\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: "=r" (res)
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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return res;
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}
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#define arch_read_trylock(lock) \
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({ unsigned long flags; \
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int res; \
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local_irq_save(flags); \
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res = __arch_read_trylock(lock); \
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local_irq_restore(flags); \
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res; \
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})
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
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#define arch_write_lock_flags(rw, flags) arch_write_lock(rw)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#define arch_read_can_lock(rw) (!((rw)->lock & 0xff))
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#define arch_write_can_lock(rw) (!(rw)->lock)
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#endif /* !(__ASSEMBLY__) */
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#endif /* __SPARC_SPINLOCK_H */
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