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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9a2a566adb
The Allwinner SoCs have on most of their GPIO banks a regulator input. This issue was mainly ignored so far because either the regulator was a static regulator that would be providing power anyway, or the bank was used for a feature unsupported so far (CSI). For the odd cases, enabling it in the bootloader was the preferred option. However, now that we are starting to support those features, and that we can't really rely on the bootloader for this, we need to model those regulators as such in the DT. This is slightly more complicated than what it looks like, since some regulators will be tied to the PMIC, and in order to have access to the PMIC bus, you need to mux its pins, which will need the pinctrl driver, that needs the regulator driver to be registered. And this is how you get a circular dependency. In practice however, the hardware cannot fall into this case since it would result in a completely unusable bus. In order to avoid that circular dependency, we can thus get and enable the regulators at pin_request time. We'll then need to account for the references of all the pins of a particular branch to know when to put the reference, but it works pretty nicely once implemented. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
349 lines
8.3 KiB
C
349 lines
8.3 KiB
C
/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __PINCTRL_SUNXI_H
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#define __PINCTRL_SUNXI_H
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#define PA_BASE 0
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#define PB_BASE 32
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#define PC_BASE 64
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#define PD_BASE 96
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#define PE_BASE 128
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#define PF_BASE 160
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#define PG_BASE 192
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#define PH_BASE 224
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#define PI_BASE 256
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#define PL_BASE 352
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#define PM_BASE 384
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#define PN_BASE 416
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#define SUNXI_PINCTRL_PIN(bank, pin) \
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PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
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#define SUNXI_PIN_NAME_MAX_LEN 5
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#define BANK_MEM_SIZE 0x24
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#define MUX_REGS_OFFSET 0x0
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#define DATA_REGS_OFFSET 0x10
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#define DLEVEL_REGS_OFFSET 0x14
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#define PULL_REGS_OFFSET 0x1c
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#define PINS_PER_BANK 32
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#define MUX_PINS_PER_REG 8
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#define MUX_PINS_BITS 4
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#define MUX_PINS_MASK 0x0f
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#define DATA_PINS_PER_REG 32
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#define DATA_PINS_BITS 1
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#define DATA_PINS_MASK 0x01
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#define DLEVEL_PINS_PER_REG 16
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#define DLEVEL_PINS_BITS 2
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#define DLEVEL_PINS_MASK 0x03
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#define PULL_PINS_PER_REG 16
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#define PULL_PINS_BITS 2
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#define PULL_PINS_MASK 0x03
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#define IRQ_PER_BANK 32
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#define IRQ_CFG_REG 0x200
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#define IRQ_CFG_IRQ_PER_REG 8
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#define IRQ_CFG_IRQ_BITS 4
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#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
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#define IRQ_CTRL_REG 0x210
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#define IRQ_CTRL_IRQ_PER_REG 32
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#define IRQ_CTRL_IRQ_BITS 1
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#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
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#define IRQ_STATUS_REG 0x214
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#define IRQ_STATUS_IRQ_PER_REG 32
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#define IRQ_STATUS_IRQ_BITS 1
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#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
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#define IRQ_DEBOUNCE_REG 0x218
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#define IRQ_MEM_SIZE 0x20
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#define IRQ_EDGE_RISING 0x00
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#define IRQ_EDGE_FALLING 0x01
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#define IRQ_LEVEL_HIGH 0x02
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#define IRQ_LEVEL_LOW 0x03
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#define IRQ_EDGE_BOTH 0x04
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#define SUN4I_FUNC_INPUT 0
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#define SUN4I_FUNC_IRQ 6
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#define PINCTRL_SUN5I_A10S BIT(1)
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#define PINCTRL_SUN5I_A13 BIT(2)
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#define PINCTRL_SUN5I_GR8 BIT(3)
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#define PINCTRL_SUN6I_A31 BIT(4)
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#define PINCTRL_SUN6I_A31S BIT(5)
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#define PINCTRL_SUN4I_A10 BIT(6)
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#define PINCTRL_SUN7I_A20 BIT(7)
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#define PINCTRL_SUN8I_R40 BIT(8)
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struct sunxi_desc_function {
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unsigned long variant;
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const char *name;
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u8 muxval;
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u8 irqbank;
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u8 irqnum;
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};
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struct sunxi_desc_pin {
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struct pinctrl_pin_desc pin;
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unsigned long variant;
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struct sunxi_desc_function *functions;
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};
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struct sunxi_pinctrl_desc {
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const struct sunxi_desc_pin *pins;
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int npins;
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unsigned pin_base;
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unsigned irq_banks;
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const unsigned int *irq_bank_map;
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bool irq_read_needs_mux;
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bool disable_strict_mode;
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};
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struct sunxi_pinctrl_function {
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const char *name;
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const char **groups;
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unsigned ngroups;
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};
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struct sunxi_pinctrl_group {
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const char *name;
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unsigned pin;
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};
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struct sunxi_pinctrl_regulator {
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struct regulator *regulator;
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refcount_t refcount;
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};
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struct sunxi_pinctrl {
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void __iomem *membase;
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struct gpio_chip *chip;
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const struct sunxi_pinctrl_desc *desc;
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struct device *dev;
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struct sunxi_pinctrl_regulator regulators[12];
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struct irq_domain *domain;
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struct sunxi_pinctrl_function *functions;
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unsigned nfunctions;
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struct sunxi_pinctrl_group *groups;
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unsigned ngroups;
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int *irq;
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unsigned *irq_array;
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raw_spinlock_t lock;
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struct pinctrl_dev *pctl_dev;
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unsigned long variant;
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};
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#define SUNXI_PIN(_pin, ...) \
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{ \
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.pin = _pin, \
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.functions = (struct sunxi_desc_function[]){ \
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__VA_ARGS__, { } }, \
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}
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#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
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{ \
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.pin = _pin, \
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.variant = _variant, \
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.functions = (struct sunxi_desc_function[]){ \
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__VA_ARGS__, { } }, \
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}
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#define SUNXI_FUNCTION(_val, _name) \
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{ \
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.name = _name, \
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.muxval = _val, \
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}
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#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
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{ \
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.name = _name, \
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.muxval = _val, \
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.variant = _variant, \
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}
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#define SUNXI_FUNCTION_IRQ(_val, _irq) \
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{ \
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.name = "irq", \
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.muxval = _val, \
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.irqnum = _irq, \
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}
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#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
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{ \
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.name = "irq", \
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.muxval = _val, \
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.irqbank = _bank, \
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.irqnum = _irq, \
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}
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/*
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* The sunXi PIO registers are organized as is:
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* 0x00 - 0x0c Muxing values.
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* 8 pins per register, each pin having a 4bits value
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* 0x10 Pin values
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* 32 bits per register, each pin corresponding to one bit
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* 0x14 - 0x18 Drive level
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* 16 pins per register, each pin having a 2bits value
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* 0x1c - 0x20 Pull-Up values
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* 16 pins per register, each pin having a 2bits value
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*
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* This is for the first bank. Each bank will have the same layout,
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* with an offset being a multiple of 0x24.
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*
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* The following functions calculate from the pin number the register
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* and the bit offset that we should access.
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*/
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static inline u32 sunxi_mux_reg(u16 pin)
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{
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u8 bank = pin / PINS_PER_BANK;
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u32 offset = bank * BANK_MEM_SIZE;
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offset += MUX_REGS_OFFSET;
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offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
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return round_down(offset, 4);
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}
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static inline u32 sunxi_mux_offset(u16 pin)
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{
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u32 pin_num = pin % MUX_PINS_PER_REG;
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return pin_num * MUX_PINS_BITS;
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}
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static inline u32 sunxi_data_reg(u16 pin)
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{
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u8 bank = pin / PINS_PER_BANK;
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u32 offset = bank * BANK_MEM_SIZE;
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offset += DATA_REGS_OFFSET;
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offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
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return round_down(offset, 4);
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}
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static inline u32 sunxi_data_offset(u16 pin)
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{
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u32 pin_num = pin % DATA_PINS_PER_REG;
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return pin_num * DATA_PINS_BITS;
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}
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static inline u32 sunxi_dlevel_reg(u16 pin)
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{
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u8 bank = pin / PINS_PER_BANK;
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u32 offset = bank * BANK_MEM_SIZE;
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offset += DLEVEL_REGS_OFFSET;
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offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
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return round_down(offset, 4);
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}
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static inline u32 sunxi_dlevel_offset(u16 pin)
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{
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u32 pin_num = pin % DLEVEL_PINS_PER_REG;
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return pin_num * DLEVEL_PINS_BITS;
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}
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static inline u32 sunxi_pull_reg(u16 pin)
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{
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u8 bank = pin / PINS_PER_BANK;
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u32 offset = bank * BANK_MEM_SIZE;
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offset += PULL_REGS_OFFSET;
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offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
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return round_down(offset, 4);
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}
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static inline u32 sunxi_pull_offset(u16 pin)
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{
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u32 pin_num = pin % PULL_PINS_PER_REG;
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return pin_num * PULL_PINS_BITS;
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}
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static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
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{
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if (!desc->irq_bank_map)
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return bank;
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else
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return desc->irq_bank_map[bank];
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}
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static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
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u16 irq)
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{
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u8 bank = irq / IRQ_PER_BANK;
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u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
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return IRQ_CFG_REG +
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sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
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}
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static inline u32 sunxi_irq_cfg_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
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return irq_num * IRQ_CFG_IRQ_BITS;
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}
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static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
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{
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return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
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}
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static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
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u16 irq)
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{
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u8 bank = irq / IRQ_PER_BANK;
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return sunxi_irq_ctrl_reg_from_bank(desc, bank);
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}
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static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
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return irq_num * IRQ_CTRL_IRQ_BITS;
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}
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static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
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{
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return IRQ_DEBOUNCE_REG +
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sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
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}
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static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
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{
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return IRQ_STATUS_REG +
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sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
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}
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static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
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u16 irq)
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{
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u8 bank = irq / IRQ_PER_BANK;
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return sunxi_irq_status_reg_from_bank(desc, bank);
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}
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static inline u32 sunxi_irq_status_offset(u16 irq)
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{
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u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
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return irq_num * IRQ_STATUS_IRQ_BITS;
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}
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int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
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const struct sunxi_pinctrl_desc *desc,
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unsigned long variant);
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#define sunxi_pinctrl_init(_dev, _desc) \
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sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
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#endif /* __PINCTRL_SUNXI_H */
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