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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ca82580c9c
LRC code was calling GEM API like i915_gem_obj_ggtt_offset from places where the struct_mutex cannot be grabbed (irq handlers). To avoid that this patch caches some interesting bits and values in the engine and context structures. Some usages are also removed where they are not needed like a few asserts which are either impossible or have been checked already during engine initialization. Side benefit is also that interrupt handlers and command submission stop evaluating invariant conditionals, like what Gen we are running on, on every interrupt and every command submitted. This patch deals with logical ring context id and descriptors while subsequent patches will deal with the remaining issues. v2: * Cache the VMA instead of the address. (Chris Wilson) * Incorporate Dave Gordon's good comments and function name. v3: * Extract ctx descriptor template to a function and group functions dealing with ctx descriptor & co together near top of the file. (Dave Gordon) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Dave Gordon <david.s.gordon@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452870629-13830-1-git-send-email-tvrtko.ursulin@linux.intel.com
124 lines
5.0 KiB
C
124 lines
5.0 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define GEN8_LR_CONTEXT_ALIGN 4096
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/* Execlists regs */
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#define RING_ELSP(ring) _MMIO((ring)->mmio_base + 0x230)
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#define RING_EXECLIST_STATUS_LO(ring) _MMIO((ring)->mmio_base + 0x234)
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#define RING_EXECLIST_STATUS_HI(ring) _MMIO((ring)->mmio_base + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(ring) _MMIO((ring)->mmio_base + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define RING_CONTEXT_STATUS_BUF_LO(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(ring) _MMIO((ring)->mmio_base + 0x3a0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
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int intel_logical_rings_init(struct drm_device *dev);
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int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
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int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
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/**
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* intel_logical_ring_advance() - advance the ringbuffer tail
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* @ringbuf: Ringbuffer to advance.
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*
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* The tail is only updated in our logical ringbuffer struct.
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*/
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static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
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{
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ringbuf->tail &= ringbuf->size - 1;
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}
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/**
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* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
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* @ringbuf: Ringbuffer to write to.
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* @data: DWORD to write.
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*/
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static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
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u32 data)
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{
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iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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ringbuf->tail += 4;
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}
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static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
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i915_reg_t reg)
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{
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intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
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}
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/* Logical Ring Contexts */
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/* One extra page is added before LRC for GuC as shared data */
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#define LRC_GUCSHR_PN (0)
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#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
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#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
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void intel_lr_context_free(struct intel_context *ctx);
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uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
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int intel_lr_context_deferred_alloc(struct intel_context *ctx,
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struct intel_engine_cs *ring);
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void intel_lr_context_unpin(struct drm_i915_gem_request *req);
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void intel_lr_context_reset(struct drm_device *dev,
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struct intel_context *ctx);
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uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
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struct intel_engine_cs *ring);
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u32 intel_execlists_ctx_id(struct intel_context *ctx,
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struct intel_engine_cs *ring);
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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struct i915_execbuffer_params;
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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struct drm_i915_gem_execbuffer2 *args,
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struct list_head *vmas);
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void intel_lrc_irq_handler(struct intel_engine_cs *ring);
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void intel_execlists_retire_requests(struct intel_engine_cs *ring);
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#endif /* _INTEL_LRC_H_ */
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