mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
c36757eb9d
After configuring and restarting aneg we immediately try to read the
link status. On some systems the PHY may not yet have cleared the
"aneg complete" and "link up" bits, resulting in a false link-up
signal. See [0] for a report.
Clause 22 and 45 both require the PHY to keep the AN_RESTART
bit set until the PHY actually starts auto-negotiation.
Let's consider this in the generic functions for reading link status.
The commit marked as fixed is the first one where the patch applies
cleanly.
[0] https://marc.info/?t=156518400300003&r=1&w=2
Fixes: c1164bb1a6 ("net: phy: check PMAPMD link status only in genphy_c45_read_link")
Tested-by: Yonglong Liu <liuyonglong@huawei.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
541 lines
14 KiB
C
541 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Clause 45 PHY support
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*/
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#include <linux/ethtool.h>
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#include <linux/export.h>
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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/**
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* genphy_c45_setup_forced - configures a forced speed
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* @phydev: target phy_device struct
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*/
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int genphy_c45_pma_setup_forced(struct phy_device *phydev)
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{
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int ctrl1, ctrl2, ret;
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/* Half duplex is not supported */
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if (phydev->duplex != DUPLEX_FULL)
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return -EINVAL;
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ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
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if (ctrl1 < 0)
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return ctrl1;
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ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
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if (ctrl2 < 0)
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return ctrl2;
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ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
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/*
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* PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
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* in 802.3-2012 and 802.3-2015.
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*/
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ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
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switch (phydev->speed) {
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case SPEED_10:
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ctrl2 |= MDIO_PMA_CTRL2_10BT;
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break;
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case SPEED_100:
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ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
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ctrl2 |= MDIO_PMA_CTRL2_100BTX;
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break;
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case SPEED_1000:
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ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
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/* Assume 1000base-T */
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ctrl2 |= MDIO_PMA_CTRL2_1000BT;
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break;
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case SPEED_2500:
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ctrl1 |= MDIO_CTRL1_SPEED2_5G;
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/* Assume 2.5Gbase-T */
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ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
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break;
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case SPEED_5000:
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ctrl1 |= MDIO_CTRL1_SPEED5G;
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/* Assume 5Gbase-T */
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ctrl2 |= MDIO_PMA_CTRL2_5GBT;
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break;
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case SPEED_10000:
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ctrl1 |= MDIO_CTRL1_SPEED10G;
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/* Assume 10Gbase-T */
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ctrl2 |= MDIO_PMA_CTRL2_10GBT;
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break;
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default:
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return -EINVAL;
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}
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ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
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if (ret < 0)
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return ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
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if (ret < 0)
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return ret;
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return genphy_c45_an_disable_aneg(phydev);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
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/**
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* genphy_c45_an_config_aneg - configure advertisement registers
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* @phydev: target phy_device struct
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*
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* Configure advertisement registers based on modes set in phydev->advertising
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*
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* Returns negative errno code on failure, 0 if advertisement didn't change,
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* or 1 if advertised modes changed.
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*/
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int genphy_c45_an_config_aneg(struct phy_device *phydev)
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{
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int changed, ret;
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u32 adv;
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linkmode_and(phydev->advertising, phydev->advertising,
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phydev->supported);
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changed = genphy_config_eee_advert(phydev);
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adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_100BASE4 |
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ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
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adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = 1;
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adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
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MDIO_AN_10GBT_CTRL_ADV10G |
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MDIO_AN_10GBT_CTRL_ADV5G |
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MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = 1;
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return changed;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
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/**
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* genphy_c45_an_disable_aneg - disable auto-negotiation
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* @phydev: target phy_device struct
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*
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* Disable auto-negotiation in the Clause 45 PHY. The link parameters
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* parameters are controlled through the PMA/PMD MMD registers.
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*
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* Returns zero on success, negative errno code on failure.
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*/
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int genphy_c45_an_disable_aneg(struct phy_device *phydev)
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{
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return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
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MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
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/**
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* genphy_c45_restart_aneg - Enable and restart auto-negotiation
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* @phydev: target phy_device struct
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*
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* This assumes that the auto-negotiation MMD is present.
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*
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* Enable and restart auto-negotiation.
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*/
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int genphy_c45_restart_aneg(struct phy_device *phydev)
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{
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return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
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MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
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/**
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* genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
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* @phydev: target phy_device struct
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* @restart: whether aneg restart is requested
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*
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* This assumes that the auto-negotiation MMD is present.
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*
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* Check, and restart auto-negotiation if needed.
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*/
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int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
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{
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int ret = 0;
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if (!restart) {
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/* Configure and restart aneg if it wasn't set before */
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
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if (ret < 0)
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return ret;
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if (!(ret & MDIO_AN_CTRL1_ENABLE))
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restart = true;
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}
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if (restart)
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ret = genphy_c45_restart_aneg(phydev);
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return ret;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
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/**
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* genphy_c45_aneg_done - return auto-negotiation complete status
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* @phydev: target phy_device struct
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*
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* This assumes that the auto-negotiation MMD is present.
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*
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* Reads the status register from the auto-negotiation MMD, returning:
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* - positive if auto-negotiation is complete
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* - negative errno code on error
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* - zero otherwise
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*/
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int genphy_c45_aneg_done(struct phy_device *phydev)
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{
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int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
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/**
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* genphy_c45_read_link - read the overall link status from the MMDs
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* @phydev: target phy_device struct
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*
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* Read the link status from the specified MMDs, and if they all indicate
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* that the link is up, set phydev->link to 1. If an error is encountered,
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* a negative errno will be returned, otherwise zero.
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*/
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int genphy_c45_read_link(struct phy_device *phydev)
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{
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u32 mmd_mask = MDIO_DEVS_PMAPMD;
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int val, devad;
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bool link = true;
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if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
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if (val < 0)
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return val;
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/* Autoneg is being started, therefore disregard current
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* link status and report link as down.
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*/
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if (val & MDIO_AN_CTRL1_RESTART) {
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phydev->link = 0;
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return 0;
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}
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}
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while (mmd_mask && link) {
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devad = __ffs(mmd_mask);
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mmd_mask &= ~BIT(devad);
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/* The link state is latched low so that momentary link
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* drops can be detected. Do not double-read the status
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* in polling mode to detect such short link drops.
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*/
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if (!phy_polling_mode(phydev)) {
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val = phy_read_mmd(phydev, devad, MDIO_STAT1);
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if (val < 0)
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return val;
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else if (val & MDIO_STAT1_LSTATUS)
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continue;
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}
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val = phy_read_mmd(phydev, devad, MDIO_STAT1);
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if (val < 0)
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return val;
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if (!(val & MDIO_STAT1_LSTATUS))
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link = false;
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}
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phydev->link = link;
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_link);
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/**
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* genphy_c45_read_lpa - read the link partner advertisement and pause
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* @phydev: target phy_device struct
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*
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* Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
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* filling in the link partner advertisement, pause and asym_pause members
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* in @phydev. This assumes that the auto-negotiation MMD is present, and
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* the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
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* to fill in the remainder of the link partner advert from vendor registers.
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*/
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int genphy_c45_read_lpa(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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if (!(val & MDIO_AN_STAT1_COMPLETE)) {
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
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phydev->lp_advertising);
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mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
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mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
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phydev->pause = 0;
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phydev->asym_pause = 0;
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return 0;
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}
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linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
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val & MDIO_AN_STAT1_LPABLE);
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/* Read the link partner's base page advertisement */
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
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if (val < 0)
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return val;
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mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
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phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
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phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
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/* Read the link partner's 10G advertisement */
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
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if (val < 0)
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return val;
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mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
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/**
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* genphy_c45_read_pma - read link speed etc from PMA
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* @phydev: target phy_device struct
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*/
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int genphy_c45_read_pma(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
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if (val < 0)
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return val;
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switch (val & MDIO_CTRL1_SPEEDSEL) {
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case 0:
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phydev->speed = SPEED_10;
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break;
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case MDIO_PMA_CTRL1_SPEED100:
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phydev->speed = SPEED_100;
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break;
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case MDIO_PMA_CTRL1_SPEED1000:
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phydev->speed = SPEED_1000;
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break;
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case MDIO_CTRL1_SPEED2_5G:
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phydev->speed = SPEED_2500;
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break;
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case MDIO_CTRL1_SPEED5G:
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phydev->speed = SPEED_5000;
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break;
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case MDIO_CTRL1_SPEED10G:
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phydev->speed = SPEED_10000;
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break;
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default:
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phydev->speed = SPEED_UNKNOWN;
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break;
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}
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phydev->duplex = DUPLEX_FULL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
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/**
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* genphy_c45_read_mdix - read mdix status from PMA
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* @phydev: target phy_device struct
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*/
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int genphy_c45_read_mdix(struct phy_device *phydev)
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{
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int val;
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if (phydev->speed == SPEED_10000) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
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MDIO_PMA_10GBT_SWAPPOL);
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if (val < 0)
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return val;
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switch (val) {
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case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
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phydev->mdix = ETH_TP_MDI;
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break;
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case 0:
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phydev->mdix = ETH_TP_MDI_X;
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break;
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default:
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phydev->mdix = ETH_TP_MDI_INVALID;
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break;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
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/**
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* genphy_c45_pma_read_abilities - read supported link modes from PMA
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* @phydev: target phy_device struct
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*
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* Read the supported link modes from the PMA Status 2 (1.8) register. If bit
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* 1.8.9 is set, the list of supported modes is build using the values in the
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* PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
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* modes. If bit 1.11.14 is set, then the list is also extended with the modes
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* in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
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* 5GBASET are supported.
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*/
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int genphy_c45_pma_read_abilities(struct phy_device *phydev)
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{
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int val;
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_AN_STAT1_ABLE)
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linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
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phydev->supported);
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}
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_STAT2_10GBSR);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_STAT2_10GBLR);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_STAT2_10GBER);
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if (val & MDIO_PMA_STAT2_EXTABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBLRM);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKX4);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKR);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BKX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_100BTX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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phydev->supported,
|
|
val & MDIO_PMA_EXTABLE_100BTX);
|
|
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
|
phydev->supported,
|
|
val & MDIO_PMA_EXTABLE_10BT);
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
|
|
phydev->supported,
|
|
val & MDIO_PMA_EXTABLE_10BT);
|
|
|
|
if (val & MDIO_PMA_EXTABLE_NBT) {
|
|
val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
|
|
MDIO_PMA_NG_EXTABLE);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
|
phydev->supported,
|
|
val & MDIO_PMA_NG_EXTABLE_2_5GBT);
|
|
|
|
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
|
|
phydev->supported,
|
|
val & MDIO_PMA_NG_EXTABLE_5GBT);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
|
|
|
|
/**
|
|
* genphy_c45_read_status - read PHY status
|
|
* @phydev: target phy_device struct
|
|
*
|
|
* Reads status from PHY and sets phy_device members accordingly.
|
|
*/
|
|
int genphy_c45_read_status(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
ret = genphy_c45_read_link(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
phydev->speed = SPEED_UNKNOWN;
|
|
phydev->duplex = DUPLEX_UNKNOWN;
|
|
phydev->pause = 0;
|
|
phydev->asym_pause = 0;
|
|
|
|
if (phydev->autoneg == AUTONEG_ENABLE) {
|
|
ret = genphy_c45_read_lpa(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
phy_resolve_aneg_linkmode(phydev);
|
|
} else {
|
|
ret = genphy_c45_read_pma(phydev);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(genphy_c45_read_status);
|
|
|
|
/* The gen10g_* functions are the old Clause 45 stub */
|
|
|
|
int gen10g_config_aneg(struct phy_device *phydev)
|
|
{
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(gen10g_config_aneg);
|
|
|
|
struct phy_driver genphy_c45_driver = {
|
|
.phy_id = 0xffffffff,
|
|
.phy_id_mask = 0xffffffff,
|
|
.name = "Generic Clause 45 PHY",
|
|
.soft_reset = genphy_no_soft_reset,
|
|
.read_status = genphy_c45_read_status,
|
|
};
|