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91bbefe6b0
MIPS is interesting and has hardware variants that reorder over ll/sc as well as those that do not. Implement the 2 new barrier functions as per the old barriers. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-9ph49jbae3hol9v721sbc2g6@git.kernel.org Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maciej W. Rozycki" <macro@codesourcery.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
202 lines
5.3 KiB
C
202 lines
5.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#include <asm/addrspace.h>
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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*/
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#ifdef CONFIG_CPU_HAS_SYNC
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#else
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#define __sync() do { } while(0)
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#endif
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
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# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
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# define fast_wmb() __syncw()
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# define fast_rmb() barrier()
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# define fast_mb() __sync()
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# define fast_iob() do { } while (0)
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#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
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# define fast_wmb() __sync()
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# define fast_rmb() __sync()
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# define fast_mb() __sync()
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# ifdef CONFIG_SGI_IP28
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# define fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"sync\n\t" \
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"lw $0,%0\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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: "memory")
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# else
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# define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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# endif
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
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# ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define smp_mb() __sync()
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# define smp_rmb() barrier()
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# define smp_wmb() __syncw()
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# else
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# define smp_mb() __asm__ __volatile__("sync" : : :"memory")
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# define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
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# define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
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# endif
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define set_mb(var, value) \
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do { var = value; smp_mb(); } while (0)
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define smp_mb__before_llsc() smp_wmb()
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/* Cause previous writes to become visible on all CPUs as soon as possible */
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#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
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".set arch=octeon\n\t" \
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"syncw\n\t" \
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".set pop" : : : "memory")
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#else
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#define smp_mb__before_llsc() smp_llsc_mb()
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#define nudge_writes() mb()
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#endif
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#define smp_mb__before_atomic() smp_mb__before_llsc()
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#define smp_mb__after_atomic() smp_llsc_mb()
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#endif /* __ASM_BARRIER_H */
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