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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4bb2d1009f
This branch contains a handful of updates of SoC base code that had dependencies on other external trees that have now been merged: * Support for the new EXYNOS5250 SoC from Samsung * SMP and power domain support for Tegra3 from NVIDIA * ux500 updates for exporting SoC information through sysfs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPcpwnAAoJEIwa5zzehBx3RIQP/AvTVHF7EIXfu5XGLBYeKW+U HBeT1kO1qL8m3gA/+DG/JzNpd8JDlILGob6hUN4lqA8f49MBkmttdbATZvBj4Nx+ T4+louPteiueexJdolj6hVCuNBhFJLgik3zMKGHvL8wbvqYHKpfqvuWWuzxtP3Hl F1BvFSrQ5TZALGtNiRWDMwxFa2oA03ZNXjy+v9i3GIdn1vH18/IDryz7/7MW6GPv NuKmZkcEpX2jDFe3AkqUMLxqMYizfuGg20FlV4tmxiF5Wlht6EiN38Y56LZgwuly mde6AWN8qgwTYDk4cJ5ZVJtwkowosF5ko57V3SPmVaVc/WajZ0v28gt9YgNLVPL7 TXFEUJgIxzJnyM+DoSltzQ9tCsWUscQGmyPt4QSOLO2D76/3z+8+24/EwAIM/7Bj u5/+74k5jDBZe1suCt/1P1Vr3l5Z3os483R7y4BtyLtWtQvBcjpkITj9lHmnsAf3 RqN2Z4osLcILwWVKa2y2DCOeJm0jvSCsn53+O3FGTSqhfwWTUVkqaDALeGXwJGbH 2rMks18BqJ2sT2ruFXHiVvZOj/8XxkcLsq8ztnuYoHQssrNtAtBM97l/xi1V7L0z FmXnPszVA1mIkelsY2VDImEks/Iaad4o3Iuba9Yr3OKOSr/d8kLyB0reTmS/SHQL u/o8ch/V5QVEo/H+ud7K =X89H -----END PGP SIGNATURE----- Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: More SoC support updates" from Olof Johansson: "This branch contains a handful of updates of SoC base code that had dependencies on other external trees that have now been merged: * Support for the new EXYNOS5250 SoC from Samsung * SMP and power domain support for Tegra3 from NVIDIA * ux500 updates for exporting SoC information through sysfs" Fix up trivial merge conflicts as per Olof. * tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits) ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board ARM: dts: add initial dts file for EXYNOS5250, SMDK5250 ARM: EXYNOS: add support device tree enabled board file for EXYNOS5 ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs ARM: EXYNOS: add support get_core_count() for EXYNOS5250 ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5 ARM: EXYNOS: add interrupt definitions for EXYNOS5250 ARM: EXYNOS: add support for EXYNOS5250 SoC ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5 ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5 ARM: EXYNOS: add clock part for EXYNOS5250 SoC ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts() ARM: EXYNOS: to declare static for mach-exynos/common.c ARM: EXYNOS: Add clkdev lookup entry for lcd clock ARM: dt: Explicitly configure all serial ports on Tegra Cardhu ARM: tegra: support for secondary cores on Tegra30 ARM: tegra: support for Tegra30 CPU powerdomains ARM: tegra: add support for Tegra30 powerdomains ARM: tegra: export tegra_powergate_is_powered() ...
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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* Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mfd/db8500-prcmu.h>
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#include <linux/mfd/db5500-prcmu.h>
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#include <linux/clksrc-dbx500-prcmu.h>
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#include <linux/sys_soc.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/stat.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/devices.h>
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#include "clock.h"
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void __iomem *_PRCMU_BASE;
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static const struct of_device_id ux500_dt_irq_match[] = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{},
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};
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void __init ux500_init_irq(void)
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{
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void __iomem *dist_base;
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void __iomem *cpu_base;
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if (cpu_is_u5500()) {
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dist_base = __io_address(U5500_GIC_DIST_BASE);
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cpu_base = __io_address(U5500_GIC_CPU_BASE);
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} else if (cpu_is_u8500()) {
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dist_base = __io_address(U8500_GIC_DIST_BASE);
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cpu_base = __io_address(U8500_GIC_CPU_BASE);
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} else
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ux500_unknown_soc();
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#ifdef CONFIG_OF
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if (of_have_populated_dt())
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of_irq_init(ux500_dt_irq_match);
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else
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#endif
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gic_init(0, 29, dist_base, cpu_base);
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/*
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* Init clocks here so that they are available for system timer
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* initialization.
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*/
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if (cpu_is_u5500())
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db5500_prcmu_early_init();
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if (cpu_is_u8500())
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db8500_prcmu_early_init();
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clk_init();
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}
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static const char * __init ux500_get_machine(void)
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{
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return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
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}
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static const char * __init ux500_get_family(void)
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{
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return kasprintf(GFP_KERNEL, "ux500");
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}
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static const char * __init ux500_get_revision(void)
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{
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unsigned int rev = dbx500_revision();
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if (rev == 0x01)
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return kasprintf(GFP_KERNEL, "%s", "ED");
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else if (rev >= 0xA0)
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return kasprintf(GFP_KERNEL, "%d.%d",
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(rev >> 4) - 0xA + 1, rev & 0xf);
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return kasprintf(GFP_KERNEL, "%s", "Unknown");
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}
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static ssize_t ux500_get_process(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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if (dbx500_id.process == 0x00)
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return sprintf(buf, "Standard\n");
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return sprintf(buf, "%02xnm\n", dbx500_id.process);
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}
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static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
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const char *soc_id)
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{
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soc_dev_attr->soc_id = soc_id;
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soc_dev_attr->machine = ux500_get_machine();
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soc_dev_attr->family = ux500_get_family();
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soc_dev_attr->revision = ux500_get_revision();
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}
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struct device_attribute ux500_soc_attr =
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__ATTR(process, S_IRUGO, ux500_get_process, NULL);
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struct device * __init ux500_soc_device_init(const char *soc_id)
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{
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struct device *parent;
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return ERR_PTR(-ENOMEM);
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soc_info_populate(soc_dev_attr, soc_id);
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR_OR_NULL(soc_dev)) {
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kfree(soc_dev_attr);
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return NULL;
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}
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parent = soc_device_to_device(soc_dev);
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if (!IS_ERR_OR_NULL(parent))
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device_create_file(parent, &ux500_soc_attr);
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return parent;
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}
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