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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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25cb3b4cf0
Calling clk_set_parent (e.g. from Ux500 ASoC-driver) generates build-errors. Signed-off-by: Ola Lilja <ola.o.lilja@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
153 lines
4.9 KiB
C
153 lines
4.9 KiB
C
/*
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* Copyright (C) 2010 ST-Ericsson
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* Copyright (C) 2009 STMicroelectronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/**
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* struct clkops - ux500 clock operations
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* @enable: function to enable the clock
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* @disable: function to disable the clock
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* @get_rate: function to get the current clock rate
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*
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* This structure contains function pointers to functions that will be used to
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* control the clock. All of these functions are optional. If get_rate is
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* NULL, the rate in the struct clk will be used.
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*/
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struct clkops {
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void (*enable) (struct clk *);
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void (*disable) (struct clk *);
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unsigned long (*get_rate) (struct clk *);
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int (*set_parent)(struct clk *, struct clk *);
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};
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/**
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* struct clk - ux500 clock structure
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* @ops: pointer to clkops struct used to control this clock
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* @name: name, for debugging
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* @enabled: refcount. positive if enabled, zero if disabled
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* @get_rate: custom callback for getting the clock rate
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* @data: custom per-clock data for example for the get_rate
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* callback
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* @rate: fixed rate for clocks which don't implement
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* ops->getrate
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* @prcmu_cg_off: address offset of the combined enable/disable register
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* (used on u8500v1)
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* @prcmu_cg_bit: bit in the combined enable/disable register (used on
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* u8500v1)
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* @prcmu_cg_mgt: address of the enable/disable register (used on
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* u8500ed)
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* @cluster: peripheral cluster number
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* @prcc_bus: bit for the bus clock in the peripheral's CLKRST
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* @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
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* -1 if no kernel clock exists.
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* @parent_cluster: pointer to parent's cluster clk struct
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* @parent_periph: pointer to parent's peripheral clk struct
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*
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* Peripherals are organised into clusters, and each cluster has an associated
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* bus clock. Some peripherals also have a parent peripheral clock.
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*
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* In order to enable a clock for a peripheral, we need to enable:
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* (1) the parent cluster (bus) clock at the PRCMU level
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* (2) the parent peripheral clock (if any) at the PRCMU level
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* (3) the peripheral's bus & kernel clock at the PRCC level
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*
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* (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
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* of the cluster and peripheral clocks, and hooking these as the parents of
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* the individual peripheral clocks.
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*
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* (3) is handled by specifying the bits in the PRCC control registers required
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* to enable these clocks and modifying them in the ->enable and
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* ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
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*
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* This structure describes both the PRCMU-level clocks and PRCC-level clocks.
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* The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
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* prcc, and parent pointers are only used for the PRCC-level clocks.
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*/
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struct clk {
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const struct clkops *ops;
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const char *name;
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unsigned int enabled;
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unsigned long (*get_rate)(struct clk *);
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void *data;
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unsigned long rate;
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struct list_head list;
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/* These three are only for PRCMU clks */
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unsigned int prcmu_cg_off;
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unsigned int prcmu_cg_bit;
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unsigned int prcmu_cg_mgt;
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/* The rest are only for PRCC clks */
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int cluster;
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unsigned int prcc_bus;
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unsigned int prcc_kernel;
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struct clk *parent_cluster;
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struct clk *parent_periph;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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struct dentry *dent_bus; /* For visible tree hierarchy */
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#endif
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};
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#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
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struct clk clk_##_name = { \
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.name = #_name, \
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.ops = &clk_prcmu_ops, \
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.prcmu_cg_off = _cg_off, \
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.prcmu_cg_bit = _cg_bit, \
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.prcmu_cg_mgt = PRCM_##_reg##_MGT \
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}
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#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
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struct clk clk_##_name = { \
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.name = #_name, \
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.ops = &clk_prcmu_ops, \
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.prcmu_cg_off = _cg_off, \
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.prcmu_cg_bit = _cg_bit, \
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.rate = _rate, \
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.prcmu_cg_mgt = PRCM_##_reg##_MGT \
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}
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#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
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struct clk clk_##_name = { \
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.name = #_name, \
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.ops = &clk_prcc_ops, \
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.cluster = _pclust, \
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.prcc_bus = _bus_en, \
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.prcc_kernel = _kernel_en, \
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.parent_cluster = &clk_per##_pclust##clk, \
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.parent_periph = _kernclk \
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}
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#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
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struct clk clk_##_name = { \
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.name = #_name, \
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.ops = &clk_prcc_ops, \
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.cluster = _pclust, \
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.prcc_bus = _bus_en, \
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.prcc_kernel = _kernel_en, \
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.parent_cluster = &clk_per##_pclust##clk, \
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.parent_periph = _kernclk, \
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.get_rate = _callback, \
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.data = (void *) _data \
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}
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#define CLK(_clk, _devname, _conname) \
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{ \
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.clk = &clk_##_clk, \
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.dev_id = _devname, \
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.con_id = _conname, \
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}
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int __init clk_db8500_ed_fixup(void);
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int __init clk_init(void);
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