mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 11:06:49 +07:00
bb0bf35452
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. The clk.h include is being included in all mxs files because it's part of mxs/clk.h even though nothing actually requires it in that file. Move the clk.h include to the C files that are actually using it and remove the clk.h include from the header file. The clkdev.h include isn't used either, so drop it too. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
177 lines
6.5 KiB
C
177 lines
6.5 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk/mxs.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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static void __iomem *clkctrl;
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static void __iomem *digctrl;
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#define CLKCTRL clkctrl
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#define DIGCTRL digctrl
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#define PLLCTRL0 (CLKCTRL + 0x0000)
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#define CPU (CLKCTRL + 0x0020)
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#define HBUS (CLKCTRL + 0x0030)
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#define XBUS (CLKCTRL + 0x0040)
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#define XTAL (CLKCTRL + 0x0050)
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#define PIX (CLKCTRL + 0x0060)
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#define SSP (CLKCTRL + 0x0070)
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#define GPMI (CLKCTRL + 0x0080)
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#define SPDIF (CLKCTRL + 0x0090)
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#define EMI (CLKCTRL + 0x00a0)
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#define SAIF (CLKCTRL + 0x00c0)
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#define TV (CLKCTRL + 0x00d0)
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#define ETM (CLKCTRL + 0x00e0)
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#define FRAC (CLKCTRL + 0x00f0)
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#define CLKSEQ (CLKCTRL + 0x0110)
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#define BP_CPU_INTERRUPT_WAIT 12
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#define BP_CLKSEQ_BYPASS_SAIF 0
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#define BP_CLKSEQ_BYPASS_SSP 5
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#define BP_SAIF_DIV_FRAC_EN 16
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#define BP_FRAC_IOFRAC 24
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static void __init clk_misc_init(void)
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{
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u32 val;
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/* Gate off cpu clock in WFI for power saving */
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writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
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/* Clear BYPASS for SAIF */
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writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
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/* SAIF has to use frac div for functional operation */
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val = readl_relaxed(SAIF);
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val |= 1 << BP_SAIF_DIV_FRAC_EN;
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writel_relaxed(val, SAIF);
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/*
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* Source ssp clock from ref_io than ref_xtal,
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* as ref_xtal only provides 24 MHz as maximum.
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*/
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writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
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/*
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* 480 MHz seems too high to be ssp clock source directly,
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* so set frac to get a 288 MHz ref_io.
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*/
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writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
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writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
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}
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static const char *const sel_pll[] __initconst = { "pll", "ref_xtal", };
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static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
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static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
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static const char *const sel_io[] __initconst = { "ref_io", "ref_xtal", };
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static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
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static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
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enum imx23_clk {
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ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
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lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
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cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
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emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
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clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
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lcdif, etm, usb, usb_phy,
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clk_max
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};
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static struct clk *clks[clk_max];
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static struct clk_onecell_data clk_data;
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static enum imx23_clk clks_init_on[] __initdata = {
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cpu, hbus, xbus, emi, uart,
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};
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static void __init mx23_clocks_init(struct device_node *np)
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{
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struct device_node *dcnp;
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u32 i;
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dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
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digctrl = of_iomap(dcnp, 0);
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WARN_ON(!digctrl);
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of_node_put(dcnp);
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clkctrl = of_iomap(np, 0);
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WARN_ON(!clkctrl);
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clk_misc_init();
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clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
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clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
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clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
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clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
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clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
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clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
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clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
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clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
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clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
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clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
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clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
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clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
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clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
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clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
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clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
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clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
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clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
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clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
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clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
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clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
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clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
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clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
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clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
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clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
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clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
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clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
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clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
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clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
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clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
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clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
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clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
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clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
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clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
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clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
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clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
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clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
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clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
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clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
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clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
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clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
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clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
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clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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if (IS_ERR(clks[i])) {
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pr_err("i.MX23 clk %d: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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return;
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}
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
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clk_prepare_enable(clks[clks_init_on[i]]);
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}
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CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);
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