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4e36de179f
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. Based on the now shared base .dtsi describing the common peripherals describe the H5 specific nodes on top of that. That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi refactor, commit message changed to meet new arm64 naming scheme, drop H3 pinctrl compatible because of interrupt bank change, drop H3 ccu compatible because of clock change, drop ccu node as it come into h3-h5 dtsi] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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| amd | ||
| amlogic | ||
| apm | ||
| arm | ||
| broadcom | ||
| cavium | ||
| exynos | ||
| freescale | ||
| hisilicon | ||
| include | ||
| lg | ||
| marvell | ||
| mediatek | ||
| nvidia | ||
| qcom | ||
| renesas | ||
| rockchip | ||
| socionext | ||
| sprd | ||
| xilinx | ||
| zte | ||
| .gitignore | ||
| Makefile | ||