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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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216ab8f155
The current slow clock rate is hardcoded. Properly get the slow clock and use its rate. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
253 lines
6.7 KiB
C
253 lines
6.7 KiB
C
/*
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* linux/arch/arm/mach-at91/at91rm9200_time.c
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2003 ATMEL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/export.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/atmel-st.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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static unsigned long last_crtr;
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static u32 irqmask;
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static struct clock_event_device clkevt;
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static struct regmap *regmap_st;
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static int timer_latch;
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/*
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* The ST_CRTR is updated asynchronously to the master clock ... but
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* the updates as seen by the CPU don't seem to be strictly monotonic.
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* Waiting until we read the same value twice avoids glitching.
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*/
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static inline unsigned long read_CRTR(void)
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{
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unsigned int x1, x2;
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regmap_read(regmap_st, AT91_ST_CRTR, &x1);
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do {
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regmap_read(regmap_st, AT91_ST_CRTR, &x2);
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if (x1 == x2)
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break;
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x1 = x2;
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} while (1);
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return x1;
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}
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
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{
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u32 sr;
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regmap_read(regmap_st, AT91_ST_SR, &sr);
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sr &= irqmask;
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/*
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* irqs should be disabled here, but as the irq is shared they are only
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* guaranteed to be off if the timer irq is registered first.
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*/
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WARN_ON_ONCE(!irqs_disabled());
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/* simulate "oneshot" timer with alarm */
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if (sr & AT91_ST_ALMS) {
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clkevt.event_handler(&clkevt);
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return IRQ_HANDLED;
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}
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/* periodic mode should handle delayed ticks */
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if (sr & AT91_ST_PITS) {
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u32 crtr = read_CRTR();
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while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
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last_crtr += timer_latch;
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clkevt.event_handler(&clkevt);
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}
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return IRQ_HANDLED;
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}
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/* this irq is shared ... */
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return IRQ_NONE;
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}
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static cycle_t read_clk32k(struct clocksource *cs)
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{
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return read_CRTR();
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}
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static struct clocksource clk32k = {
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.name = "32k_counter",
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.rating = 150,
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.read = read_clk32k,
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.mask = CLOCKSOURCE_MASK(20),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void clkdev32k_disable_and_flush_irq(void)
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{
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unsigned int val;
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/* Disable and flush pending timer interrupts */
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regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
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regmap_read(regmap_st, AT91_ST_SR, &val);
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last_crtr = read_CRTR();
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}
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static int clkevt32k_shutdown(struct clock_event_device *evt)
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{
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clkdev32k_disable_and_flush_irq();
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irqmask = 0;
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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static int clkevt32k_set_oneshot(struct clock_event_device *dev)
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{
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clkdev32k_disable_and_flush_irq();
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/*
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* ALM for oneshot irqs, set by next_event()
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* before 32 seconds have passed.
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*/
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irqmask = AT91_ST_ALMS;
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regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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static int clkevt32k_set_periodic(struct clock_event_device *dev)
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{
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clkdev32k_disable_and_flush_irq();
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/* PIT for periodic irqs; fixed rate of 1/HZ */
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irqmask = AT91_ST_PITS;
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regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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static int
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clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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u32 alm;
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int status = 0;
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unsigned int val;
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BUG_ON(delta < 2);
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/* The alarm IRQ uses absolute time (now+delta), not the relative
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* time (delta) in our calling convention. Like all clockevents
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* using such "match" hardware, we have a race to defend against.
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*
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* Our defense here is to have set up the clockevent device so the
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* delta is at least two. That way we never end up writing RTAR
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* with the value then held in CRTR ... which would mean the match
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* wouldn't trigger until 32 seconds later, after CRTR wraps.
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*/
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alm = read_CRTR();
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/* Cancel any pending alarm; flush any pending IRQ */
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regmap_write(regmap_st, AT91_ST_RTAR, alm);
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regmap_read(regmap_st, AT91_ST_SR, &val);
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/* Schedule alarm by writing RTAR. */
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alm += delta;
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regmap_write(regmap_st, AT91_ST_RTAR, alm);
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return status;
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}
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static struct clock_event_device clkevt = {
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.name = "at91_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.rating = 150,
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.set_next_event = clkevt32k_next_event,
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.set_state_shutdown = clkevt32k_shutdown,
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.set_state_periodic = clkevt32k_set_periodic,
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.set_state_oneshot = clkevt32k_set_oneshot,
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.tick_resume = clkevt32k_shutdown,
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};
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/*
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* ST (system timer) module supports both clockevents and clocksource.
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*/
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static void __init atmel_st_timer_init(struct device_node *node)
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{
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struct clk *sclk;
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unsigned int sclk_rate, val;
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int irq, ret;
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regmap_st = syscon_node_to_regmap(node);
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if (IS_ERR(regmap_st))
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panic(pr_fmt("Unable to get regmap\n"));
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/* Disable all timer interrupts, and clear any pending ones */
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regmap_write(regmap_st, AT91_ST_IDR,
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AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
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regmap_read(regmap_st, AT91_ST_SR, &val);
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/* Get the interrupts property */
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irq = irq_of_parse_and_map(node, 0);
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if (!irq)
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panic(pr_fmt("Unable to get IRQ from DT\n"));
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/* Make IRQs happen for the system timer */
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ret = request_irq(irq, at91rm9200_timer_interrupt,
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IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
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"at91_tick", regmap_st);
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if (ret)
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panic(pr_fmt("Unable to setup IRQ\n"));
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sclk = of_clk_get(node, 0);
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if (IS_ERR(sclk))
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panic(pr_fmt("Unable to get slow clock\n"));
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clk_prepare_enable(sclk);
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if (ret)
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panic(pr_fmt("Could not enable slow clock\n"));
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sclk_rate = clk_get_rate(sclk);
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if (!sclk_rate)
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panic(pr_fmt("Invalid slow clock rate\n"));
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timer_latch = (sclk_rate + HZ / 2) / HZ;
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/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
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* directly for the clocksource and all clockevents, after adjusting
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* its prescaler from the 1 Hz default.
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*/
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regmap_write(regmap_st, AT91_ST_RTMR, 1);
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/* Setup timer clockevent, with minimum of two ticks (important!!) */
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clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&clkevt, sclk_rate,
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2, AT91_ST_ALMV);
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/* register clocksource */
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clocksource_register_hz(&clk32k, sclk_rate);
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}
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CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
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atmel_st_timer_init);
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